Unified Layer Stack Architecture for IC Design Automation
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Solution Overview
Problem
The existing integrated circuit design process requires designers to manually create multiple specific stack designs for different integrated circuit families, which is time-consuming and costly, and involves significant engineering effort to maintain and update these designs.
Innovation Solution
A method where a programmed computing system automatically processes a highest level integrated circuit design to selectively remove metal layers and map remaining layers, generating all necessary lower level designs without user intervention, thereby reducing the need for manual creation and maintenance of multiple designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple specific stack designs are manually created for different integrated circuit families, then design flexibility and customization are improved, but engineering time and cost increase significantly
Solution Approach 1:
The patent creates a universal highest level design that can serve multiple integrated circuit families through automatic layer removal and mapping. Instead of creating separate designs for each family, a single highest level design with 7 bottom metal layers and 2 top metal layers can be automatically transformed into various lower level designs (5+1, 5+2, 6+1, 6+2, 7+1, 7+2) by selectively removing metal layers and remapping connections, thereby achieving universality across different design requirements
Solution Approach 2:
The patent performs preliminary action by creating the complete highest level design first, with all metal layers and connections already established. This preliminary design serves as a master template from which all lower level designs can be derived through automatic processing, eliminating the need to manually create each design from scratch and significantly reducing engineering time
2Adaptability or versatility
If multiple specific stack designs are manually created for different integrated circuit families, then design customization is improved, but maintenance and update effort increase
Solution Approach 1:
The universal highest level design acts as a single source of truth for the entire design family. When design updates or corrections are needed, changes are made only in the highest level design, and the automatic layer removal and mapping process propagates these updates to all lower level designs, eliminating the need to manually update multiple separate designs and significantly reducing maintenance effort
Solution Approach 2:
The patent merges multiple design variations into a single highest level design structure. By combining all metal layers (7 bottom + 2 top) into one comprehensive design, the system eliminates the need to maintain separate designs for different configurations, thereby simplifying maintenance while preserving customization capabilities through selective layer removal
3Manufacturing precision
If manual creation of multiple stack designs is performed, then design specificity is improved, but productivity decreases
Solution Approach 1:
The system performs self-service by automatically generating lower level designs from the highest level design without requiring manual intervention for each design variation. The automatic layer removal and mapping processes handle the creation of multiple design-specific configurations autonomously, maintaining design specificity while dramatically improving productivity by eliminating repetitive manual work
Solution Approach 2:
The patent uses copying by creating lower level designs as derived versions of the highest level design. Instead of manually recreating designs, the system automatically copies and adapts the highest level design structure, selectively removing metal layers and remapping connections to produce design-specific variations, thereby maintaining precision while enhancing productivity
Data Source
AI summary
A method for producing a family of digital integrated circuit designs, where the family has a highest level design and at least one lower level design. The highest level design is first produced. Then, in a programmed computing system without user intervention, the highest level design is automatically processed to selectively remove at least one predetermined metal layer. A closest remaining overlying layer to the at least one removed metal layer is automatically mapped to a closest remaining underlying layer to the at least one removed metal layer, thereby producing the at least one lower level design.