Unified Memory Architecture for Processor In-Package and Platform Memory
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Solution Overview
Problem
In computer systems, existing memory architectures face challenges with high latency and inefficiency due to the separation of memory types, particularly as form factors shrink, making it difficult to effectively utilize high-bandwidth in-package memory alongside traditional off-package memory.
Innovation Solution
The solution involves configuring both high-bandwidth memory (MCDRAM) and DDR memory as part of a unified memory space using Non-Uniform Memory Architecture (NUMA) mechanisms, allowing software to manage and allocate memory across these types seamlessly, with caching and hybrid modes to optimize performance and bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory is located outside the processor package (platform memory), then memory capacity is increased, but access latency increases
Solution Approach 1:
The memory system is segmented into two distinct types: in-package memory (MCDRAM) and off-package memory (DDR). Each segment serves different purposes - MCDRAM provides low-latency access for critical data while DDR provides high capacity for bulk storage. The memory controller automatically segments memory allocations between these two types based on access patterns and requirements.
2Productivity
If in-package memory is used, then access bandwidth is increased, but memory management complexity increases
Solution Approach 1:
The system implements self-service memory management where the memory controller automatically determines whether to allocate memory in MCDRAM or DDR based on workload characteristics, access patterns, and system state. Software can issue simple allocation requests without needing to manually manage the complexity of heterogeneous memory types, as the system self-adapts to optimize performance.
Solution Approach 2:
The memory subsystem is designed with multi-functionality to handle both high-bandwidth MCDRAM and high-capacity DDR through a unified interface. The memory controller provides universal memory management capabilities that work seamlessly across both memory types, allowing software to treat them as a unified resource pool while maintaining optimized access paths.
3Productivity
If separate memory types are used (MCDRAM and DDR), then performance is improved for specific workloads, but software portability and ease of use deteriorate
Solution Approach 1:
The patent merges MCDRAM and DDR into a unified memory space with a common address namespace. Software interacts with a single virtual memory pool without needing to know whether data resides in MCDRAM or DDR. The memory controller transparently manages the physical location of data, combining the benefits of both memory types while maintaining software portability and simplicity.
Data Source
AI summary
In one embodiment, a processor comprises: at least one core formed on a die to execute instructions; a first memory controller to interface with an in-package memory; a second memory controller to interface with a platform memory to couple to the processor; and the in-package memory located within a package of the processor, where the in-package memory is to be identified as a more distant memory with respect to the at least one core than the platform memory. Other embodiments are described and claimed.