Unified Memory Bus for Multi-Class Data Fetching
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Solution Overview
Problem
Current memory systems face inefficiencies in utilizing multiple memory technologies effectively, leading to suboptimal performance and resource utilization due to the lack of a unified approach for managing different memory classes on a single memory bus.
Innovation Solution
A physical memory system is designed to include a first physical memory of one class and a second physical memory of another class, communicatively coupled to facilitate efficient data transfer and management, allowing for the use of a single memory bus to handle instructions from a CPU, thereby optimizing memory operations across different memory technologies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple memory classes are managed separately on different buses, then each memory class can be optimized independently, but the overall system complexity increases and resource utilization becomes suboptimal
Solution Approach 1:
The patent merges multiple memory classes (DRAM and non-volatile memory) onto a single memory bus, allowing both memory types to share the same communication pathway. This consolidation reduces system complexity by eliminating separate bus infrastructures while maintaining the ability to optimize each memory class through independent controller management and time-division multiplexing protocols.
Solution Approach 2:
The unified memory bus is designed to be universal, capable of handling multiple memory classes with different access patterns and performance requirements. The bus incorporates time-division multiplexing and priority-based arbitration mechanisms that enable a single physical bus to serve multiple memory types effectively, making the system more versatile without proportionally increasing complexity.
2Productivity
If a single memory bus is used for multiple memory classes, then resource utilization improves and system complexity reduces, but memory access conflicts and timing issues increase
Solution Approach 1:
The memory bus incorporates dynamic time-division multiplexing that adjusts access timing based on real-time memory class requirements. The system dynamically allocates bus cycles between DRAM and non-volatile memory accesses, using priority-based arbitration and variable timing protocols to prevent conflicts and maintain reliable access patterns for each memory type despite sharing the same physical bus.
3Adaptability or versatility
If different memory technologies are used without unified management, then system flexibility is maintained, but operational overhead increases and performance optimization is limited
Solution Approach 1:
The unified memory management system incorporates feedback mechanisms that monitor memory access patterns, throughput, and latency for different memory classes. Based on this feedback, the system dynamically adjusts time-division scheduling, priority levels, and buffer allocations to optimize performance while reducing operational overhead through automated management rather than manual configuration.
Data Source
AI summary
A computer program product, apparatus and associated method/processing unit are provided for utilizing a physical memory system including a first physical memory of a first physical memory class, and a second physical memory of a second physical memory class communicatively coupled to the first physical memory. In operation, one or more pages are fetched from the first physical memory using a time between an execution of a plurality of threads associated with the second physical memory.