Unified Memory Cell With Segmented Stacked Gates
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Solution Overview
Problem
Conventional memory technologies face limitations in terms of speed, power consumption, capacity, and durability, particularly in silicon-based non-volatile one-transistor memory cells, which restrict their application across different levels of memory hierarchy (L1 to L5) due to high programming voltages, low endurance, and scalability issues.
Innovation Solution
The development of silicon-based unified memory (SUM) cells that integrate a field-effect transistor with a dielectric stack, allowing for scalable, low-power, and high-reliability non-volatile memory operation across various memory levels by varying the dielectric stack design to achieve different functionalities, including reduced programming voltages and enhanced endurance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional silicon-based non-volatile one-transistor memory cells are used, then non-volatile storage is achieved, but high programming voltages and low endurance result
Solution Approach 1:
The patent changes the electrical parameters of the memory cell by introducing a stacked gate structure with controlled gate lengths (LG1, LG2) and gate voltages (VGG1, VGG2). This enables independent control of programming and erasing operations, reducing the overall programming voltage requirement while improving endurance through optimized field distribution across the floating gate and oxide layer.
Solution Approach 2:
The control gate is segmented into two independent gates (first stacked gate and second stacked gate) with different gate lengths and voltage controls. This segmentation allows separate optimization of programming and erasing functions, enabling low-voltage operation while maintaining high reliability and endurance performance.
2Quantity of substance
If memory capacity is increased, then storage capacity improves, but programming speed decreases
Solution Approach 1:
The patent employs dynamic voltage control on the two stacked gates, where VGG1 and VGG2 can be independently adjusted during programming and erasing operations. This dynamic control enables faster charge injection and removal rates, improving programming speed while maintaining the ability to scale memory capacity through increased cell density.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
SUM cells offer higher programming speed, lower power consumption, and increased endurance, enabling them to replace conventional memories in digital systems and eliminate the need for a hierarchical memory structure, thus improving system performance and reliability.
Implementation Method 1
the first stacked gate and the second stacked gate are independently controllable such that the first stacked gate and the second stacked gate are used to program and erase the memory cell
Implementation Method 2
the first stacked gate and the second stacked gate are independently controllable such that the first stacked gate and the second stacked gate are used to program and erase the memory cell
Data Source
AI summary
In an example, a memory cell may have an interface dielectric adjacent to a semiconductor, a tunnel dielectric adjacent to the interface dielectric, a charge trap adjacent to the tunnel dielectric, a blocking dielectric adjacent to the charge trap, and a control gate adjacent to the blocking dielectric.