Silicon-Based Unified Memory Cells Vertical Channel Design
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Solution Overview
Problem
Conventional memory technologies face limitations in achieving high bit density, stability of data states, and endurance due to short-channel effects and the need for hierarchical memory organization, which complicates scalability and increases power consumption.
Innovation Solution
The development of silicon-based unified memory (SUM) cells with a unique dielectric stack design that integrates a field-effect transistor (FET) with a charge storage capability, allowing for vertical channel implementation and scalable gate stack designs to achieve multilevel cell (MLC) functionality without short-channel effects, enabling higher bit density and improved retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional horizontal channel memory cells are used, then manufacturing is simpler, but short-channel effects increase and bit density is limited
Solution Approach 1:
The patent transitions from conventional horizontal channel memory cells to vertical channel memory cells, changing the spatial dimension of the channel from lateral to vertical orientation. This dimensional change allows the channel to extend perpendicular to the substrate surface, enabling higher bit density while maintaining longer channel lengths that reduce short-channel effects. The vertical channel structure with gate electrodes wrapping around the channel from multiple directions provides enhanced control over the charge carrier flow.
2Stability of the object's composition
If hierarchical memory organization is implemented, then data stability is improved, but device complexity and power consumption increase
Solution Approach 1:
The patent describes unified memory cells that can operate in multiple modes (volatile and non-volatile) without requiring separate hierarchical memory structures. The memory cell uses a universal structure with gate electrodes, channel, and charge storage capability that can function as SRAM, DRAM, or flash memory depending on the operational mode, eliminating the need for complex hierarchical organization while maintaining data stability through controlled charge storage and retention mechanisms.
3Reliability
If more gate electrodes are added to control vertical channel, then channel control is improved, but device complexity increases
Solution Approach 1:
The patent employs an asymmetric gate electrode configuration where different gate electrodes (first gate electrode, second gate electrode, third gate electrode) are positioned at different locations relative to the vertical channel and serve different control functions. This asymmetric arrangement allows optimized control of charge carriers from multiple directions without requiring a symmetric complex structure, achieving reliable channel control while managing device complexity through functional differentiation of each gate electrode.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution provides increased bit density, reduced short-channel effects, improved data retention, and lower power consumption by employing a vertical channel implementation and novel gate stack designs, enhancing the performance and reliability of memory cells across various memory levels.
Implementation Method 1
A memory cell of the series-coupled memory cells may have an access gate, a control gate coupled to the access gate, and a dielectric stack between the control gate and a semiconductor. The dielectric stack may be to store a charge.
Data Source
AI summary
In an example, a memory may have a group of series-coupled memory cells, where a memory cell of the series-coupled memory cells has an access gate, a control gate coupled to the access gate, and a dielectric stack between the control gate and a semiconductor. The dielectric stack is to store a charge.