Unified Memory Controller for Heterogeneous Access Units
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing memory devices face challenges in efficiently managing and controlling operations across different types of memories with varying form factors and access units, requiring distinct control schemes and error correction codes, which complicates data transfer and storage.
Innovation Solution
A memory device with a controller that manages data operations based on different access units, using a storage circuit to store information about each access unit, and a media controller that compares write request packets to queue them appropriately, allowing for unified control and error correction across multiple memory types.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a memory device includes multiple types of memories with different form factors and access units, then the memory device can support diverse memory operations, but the controller must manage different control schemes and error correction codes for each memory type, increasing system complexity
Solution Approach 1:
The controller is designed with a universal control architecture that can handle multiple memory types (DDR3, DDR4, LPDDR3, LPDDR4) through a single unified control scheme. The controller includes a storage circuit that stores access unit information for different memory types and dynamically configures its operation based on the detected memory type, eliminating the need for separate control schemes for each memory type while maintaining full compatibility
Solution Approach 2:
A storage circuit is introduced as an intermediary component that stores access unit information for different memory types. This storage circuit acts as a mediator between the controller and various memory types, providing the controller with the necessary configuration data to adapt to different memory form factors and access units without increasing control complexity
2Productivity
If the controller manages data operations based on different access units for various memory types, then data transfer efficiency is improved, but the host must generate specific commands for each access unit, increasing host burden
Solution Approach 1:
The controller autonomously detects the memory type and retrieves the corresponding access unit information from its storage circuit. It then automatically configures its data operations based on the detected memory type without requiring the host to generate specific commands for each access unit. This self-service capability maintains high data transfer efficiency while significantly reducing the host's operational burden
Solution Approach 2:
The storage circuit pre-stores access unit information for multiple memory types before the controller needs to operate them. This preliminary preparation allows the controller to quickly configure itself when a memory device is detected, eliminating the need for the host to manually configure access units and enabling efficient data transfer from the outset
3Ease of operation
If the controller uses unified control for multiple memory types, then ease of operation is improved, but compatibility of error correction schemes across different memory types becomes challenging
Solution Approach 1:
The controller dynamically changes its error correction parameters based on the detected memory type. The storage circuit stores error correction information specific to each memory type (DDR3, DDR4, LPDDR3, LPDDR4), and the controller automatically applies the appropriate error correction scheme when operating with each memory type. This parameter adaptation maintains unified control operation while ensuring error correction compatibility across all memory types
Data Source
AI summary
A memory device includes a plurality of memories, a plurality of access units and a controller configured to control data from an access unit according to an operation cycle of another access unit whose form factor is different from that of the access unit.