Unified Memory Architecture for CPU-GPU Data Transfer
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Solution Overview
Problem
Current operating systems manage GPUs as I/O devices rather than processors, leading to separate physical address domains for CPUs and GPUs, resulting in inefficient data transfer when offloading computational tasks, which reduces the efficiency gains from task offloading to GPUs.
Innovation Solution
Implementing a unified memory architecture (UMA) that shares the same physical memory and address space between CPUs and GPUs, allowing direct access and modification without data copying, by mapping virtual memory addresses to physical memory pages and using a last level cache for coherence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If GPUs are managed as I/O devices with separate physical address domains, then device management simplicity is improved, but data transfer efficiency deteriorates due to required data copying
Solution Approach 1:
The patent merges the CPU and GPU physical address domains into a unified address space, allowing both processors to access the same physical memory without data copying. This resolves the contradiction by combining previously separate address domains while maintaining management simplicity through a unified memory architecture.
Solution Approach 2:
The unified address space serves multiple functions: it acts as both the CPU address domain and GPU address domain simultaneously, eliminating the need for separate physical memory spaces. This multi-functionality allows the same address space to serve both processors directly, improving data transfer efficiency while maintaining operational simplicity.
2Reliability
If data is copied between CPU memory and GPU memory during task offloading, then data coherence is ensured, but data transfer time increases
Solution Approach 1:
The patent extracts the data copying step from the task offloading process by implementing direct access to shared physical memory. By removing the intermediate copying operation while maintaining coherence through cache synchronization mechanisms, the system achieves both time efficiency and data coherence.
Solution Approach 2:
The last level cache serves as an intermediary that maintains data coherence between CPU and GPU operations on shared memory. This mediator ensures that modifications by one processor are visible to the other without requiring explicit data copying, thus maintaining reliability while reducing transfer time.
3Reliability
If data is copied between CPU and GPU memory, then memory isolation is maintained, but power consumption increases
Solution Approach 1:
The patent merges CPU and GPU memory access into a single shared physical memory space, eliminating the energy-intensive data copying operation. Virtual memory mechanisms maintain logical isolation and protection while physical memory is shared, thus reducing power consumption while maintaining memory safety through virtual address translation.
4Device complexity
If separate physical memory spaces are used for CPU and GPU, then address space management is simplified, but overall system memory utilization deteriorates
Solution Approach 1:
The unified address space serves both CPU and GPU simultaneously, allowing the same physical memory to be utilized by both processors. This multi-functionality maximizes memory utilization while virtual memory management maintains the simplicity of address space allocation and protection for each processor type.
Data Source
AI summary
A method and system for sharing memory between a central processing unit (CPU) and a graphics processing unit (GPU) of a computing device are disclosed herein. The method includes allocating a surface within a physical memory and mapping the surface to a plurality of virtual memory addresses within a CPU page table. The method also includes mapping the surface to a plurality of graphics virtual memory addresses within an I/O device page table.