Unified Memory Interface Reducing Channel Occupation

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Solution Overview

Problem

Current data processing systems face inefficiencies due to the incompatibility between dynamic random access memory (DRAM) and flash memory devices, leading to increased power consumption and reduced operating speed and latency.

Innovation Solution

A memory sub-system with a common interface unit that controls both main memory and storage devices, allowing for unified access and management through a control unit, which includes features like page mapping, synchronization, and buffer management to optimize data transfer and reduce channel occupation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If separate control interfaces are used for DRAM and flash memory devices, then each memory type can be independently controlled, but power consumption increases and system performance decreases

Engineering Contradiction:
Improvememory compatibilityVSAvoidpower consumption
Core Design Contradiction:
Adaptability or versatilityVSUse of energy by moving object

Solution Approach 1:

The patent combines separate control interfaces for DRAM and flash memory into a single unified interface. The interface unit receives commands from the host and determines whether to access main memory or storage device, eliminating the need for separate control logic and reducing overall power consumption while maintaining compatibility with both memory types.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The unified interface unit is designed to handle multiple memory types (DRAM and flash memory) through a single interface. It can interpret commands for both memory types and route them appropriately, making the interface universal and reducing the need for multiple specialized control paths that would increase power consumption.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If separate control interfaces are used for DRAM and flash memory devices, then each memory type can be independently controlled, but operating speed and latency are reduced

Engineering Contradiction:
Improvememory compatibilityVSAvoidoperating speed
Core Design Contradiction:
Adaptability or versatilityVSSpeed

Solution Approach 1:

By merging control interfaces into a unified structure, the patent eliminates the latency associated with switching between separate control paths. The interface unit can directly route commands to the appropriate memory type without going through multiple interface layers, improving operating speed while maintaining support for both DRAM and flash memory.

Inventive Principle:
Principle #5Merging (Combining)

3Adaptability or versatility

If multiple control interfaces are used for main memory and storage device, then each can be optimized independently, but channel occupation increases

Engineering Contradiction:
Improvememory optimizationVSAvoidinterface complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent merges multiple control interfaces into a single interface unit that handles both main memory and storage device access. This reduces channel occupation and interface complexity while maintaining the ability to optimize access patterns for different memory types through intelligent command routing and buffer management within the unified interface.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9244824B2Memory sub-system and computing system including the same
Publication Date: 2016.01.26 SAMSUNG ELECTRONICS CO LTD
  • US9244824B2 patent drawing
  • US9244824B2 patent drawing
  • US9244824B2 patent drawing

AI summary

A memory sub-system includes a main memory, a storage device, a control unit, and a common interface unit. The control unit is configured to control the main memory and the storage device. The common interface unit is operatively coupled to the control unit, and is configured to access the main memory and the storage device through the control unit in response to a request received from a host.