Heterogeneous Processor-Accelerator Processing with Unified Memory
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Solution Overview
Problem
The existing heterogeneous systems face inefficiencies in data processing due to the large number of interactions between processors and accelerators, which are connected via high-speed serial computer expansion buses, leading to increased data transfer and processing times.
Innovation Solution
The system employs a cache coherence bus to connect processors and accelerators, allowing unified addressing and direct data transfer between primary, secondary memories, and accelerators, reducing the need for intermediate data migrations and notifications, and enabling direct processing and result writing in secondary memory.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the processor and accelerator are connected via PCIE bus with separate primary and secondary memories, then the system architecture is well-defined and stable, but the data processing efficiency deteriorates due to multiple DMA migrations and notifications
Solution Approach 1:
The patent merges the primary memory and secondary memory into a unified memory space that is directly accessible by both the processor and accelerator. This eliminates the need for separate memory spaces and the complex DMA migration process between them, thereby improving data processing efficiency while maintaining system stability through a well-defined unified memory architecture.
Solution Approach 2:
The patent introduces a unified memory space as an intermediary that facilitates direct data sharing between the processor and accelerator. This unified memory acts as a mediator that eliminates the need for multiple notification and migration steps, allowing the processor to directly access data needed by the accelerator and vice versa, thus improving processing efficiency without compromising system reliability.
2Measurement precision
If the processor notifies the accelerator multiple times for data migration and processing, then data accuracy is ensured through proper coordination, but the processing time increases due to frequent interactions
Solution Approach 1:
The patent implements preliminary action by having the processor directly write data into the unified memory space in advance, making it immediately accessible to the accelerator without requiring intermediate notification steps. This preliminary data placement ensures data accuracy is maintained while eliminating time-consuming notification and migration interactions.
Solution Approach 2:
The patent extracts the notification and data migration steps from the data processing workflow. By using a unified memory space, the system removes the need for repeated notifications about data migration, keeping only the essential processing operations. This extraction maintains data accuracy through proper memory management while significantly reducing processing time.
3Device complexity
If data is migrated between primary and secondary memory through DMA, then memory architecture is well-organized with clear separation of duties, but the number of processing steps increases
Solution Approach 1:
The patent merges the previously separate primary and secondary memory systems into a unified memory space that maintains clear organizational structure while eliminating the need for DMA migration steps. The unified memory preserves the logical separation of duties between processor and accelerator memory spaces but removes the physical migration requirement, thereby reducing processing steps while maintaining architectural organization.
Solution Approach 2:
The unified memory space serves multiple functions simultaneously: it acts as both the processor's working memory and the accelerator's data source, eliminating the need for separate primary and secondary memory systems. This multi-functionality reduces the number of processing steps required for data migration while maintaining the organizational benefits of a well-structured memory architecture.
Data Source
AI summary
A data processing method and apparatus, and a heterogeneous system, pertaining to the field of computer technologies are provided. The heterogeneous system includes a processor connected to an accelerator. A secondary memory is connected to the accelerator. The processor is configured to write to-be-processed data into the secondary memory and trigger the accelerator to access and process the to-be-processed data stored in the secondary memory according to a processing instruction. The accelerator is configured to write a processing result of the to-be-processed data into the secondary memory and to trigger the processor to read the processing result. Processing efficiency is enhanced by reducing the number of times of interaction between the processor and the accelerator and simplifying the procedure for data processing.