Unified Memory SoC Architecture for Scalable Multi-Die Computing
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Solution Overview
Problem
Conventional system-on-a-chip (SOC) designs are individually architected for specific applications, leading to limited design reuse and duplicated effort across different implementations, and there is a need for a scalable design that can adapt to varying compute requirements and power constraints.
Innovation Solution
A scalable SOC design featuring a unified memory architecture with a unified address space that allows heterogeneous agents to collaborate, along with an interconnect fabric that supports scalability and transparent integration across single or multiple dies, enabling easy scaling from small to large applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional individually-architected SOCs are designed for specific applications, then the system can be optimized for that application, but design reuse is limited and development effort is duplicated
Solution Approach 1:
The patent implements a universal SOC architecture with a standardized set of heterogeneous agents (processors, memory controllers, peripherals) that can be configured for different applications through software rather than hardware redesign. The unified memory architecture and scalable interconnect fabric serve multiple functions across different device types, eliminating the need for separate hardware designs for each application scenario.
Solution Approach 2:
The SOC is divided into modular heterogeneous agents that can be independently configured and scaled. The architecture allows selective inclusion of different agent types and numbers based on application requirements, enabling design reuse by reconfiguring the same modular components rather than redesigning the entire system for each application.
2Adaptability or versatility
If the SOC is designed to be scalable from small to large applications, then adaptability improves, but the architecture complexity increases
Solution Approach 1:
The scalable architecture uses a universal set of heterogeneous agents and a unified memory architecture that works across all scaling levels. The same basic agent types and interconnect mechanisms serve both small embedded applications and larger systems, allowing scalability without proportionally increasing architectural complexity.
Solution Approach 2:
The architecture provides dynamic scalability through software-configurable resource allocation rather than fixed hardware designs. The system can dynamically adjust the number and configuration of heterogeneous agents based on workload requirements, enabling flexible scaling from single-core to multi-core configurations without hardware redesign.
3Productivity
If a unified memory architecture is implemented, then heterogeneous agents can collaborate efficiently, but the interconnect fabric complexity increases
Solution Approach 1:
The unified memory architecture provides a universal memory access interface that all heterogeneous agents use consistently. This standardization enables efficient collaboration by simplifying memory addressing and access protocols across different agent types, reducing the need for complex agent-specific memory subsystems.
Solution Approach 2:
Multiple memory access paths and control mechanisms are merged into a single unified memory architecture. This consolidation simplifies the interconnect fabric by providing a common memory interface that all agents share, reducing redundancy and complexity compared to separate memory subsystems for different agent types.
Data Source
AI summary
Techniques are disclosed related to a scalable system on a chip (SOC). In some embodiments, a system includes a plurality of processor cores, a plurality of graphics processing units, a plurality of peripheral circuits, and a plurality of memory controllers configured to support scaling of the system using a unified memory architecture.