Unified Miss Handler for Distributed Cache Segmentation

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Solution Overview

Problem

Current computing architectures with a single unified L1 cache result in inferior single-threaded performance, high latency, and inefficient cache access energy due to the limitations of unified cache management.

Innovation Solution

A unified miss handler is introduced to manage miss requests from distributed local caches, merging smaller cache line size requests into wider ones, performing hit/miss detection, and handling data retrieval from L2 cache or DRAM, thereby reducing the need for miss-handling state and data storage in local caches.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single unified L1 cache is used with multiple lanes, then cache structure is simplified, but single-threaded performance and cache access efficiency deteriorate

Engineering Contradiction:
Improvecache structureVSAvoidsingle-threaded performance
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The L1 cache is segmented into multiple distributed local caches (one per lane), each independently managing its own cache lines. This segmentation allows each lane to have dedicated cache resources, improving single-threaded performance while maintaining overall system simplicity through the unified miss handler that manages all segments.

Inventive Principle:
Principle #1Segmentation

2Device complexity

If a single unified L1 cache is used with multiple lanes, then cache structure is simplified, but access latency increases

Engineering Contradiction:
Improvecache structureVSAvoidaccess latency
Core Design Contradiction:
Device complexityVSLoss of time

Solution Approach 1:

By segmenting the unified cache into distributed local caches per lane, each cache can independently handle hits without contention from other lanes, reducing access latency for local hits while the unified miss handler manages miss requests efficiently.

Inventive Principle:
Principle #1Segmentation

3Device complexity

If a single unified L1 cache is used with multiple lanes, then cache structure is simplified, but cache access energy efficiency deteriorates

Engineering Contradiction:
Improvecache structureVSAvoidcache access energy
Core Design Contradiction:
Device complexityVSUse of energy by moving object

Solution Approach 1:

Segmenting the cache into distributed local caches reduces energy consumption by allowing lanes to access their local caches independently without interfering with other lanes, reducing unnecessary memory accesses and energy waste from cache conflicts.

Inventive Principle:
Principle #1Segmentation

4Productivity

If distributed local caches are used instead of unified cache, then single-threaded performance improves, but device complexity increases

Engineering Contradiction:
Improvesingle-threaded performanceVSAvoidcache management structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The unified miss handler acts as an intermediary that manages all miss requests from distributed local caches. It provides a centralized coordination mechanism that simplifies the complexity of managing multiple distributed caches, handling miss requests, and coordinating with L2 cache or DRAM while allowing each local cache to operate independently for high performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

5Area of stationary object

If distributed local caches are used, then area efficiency improves by eliminating miss-handling state storage, but cache management complexity increases

Engineering Contradiction:
Improvearea efficiencyVSAvoidcache management structure
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The miss-handling state and data storage are extracted from the distributed local caches and centralized in the unified miss handler. This extraction frees up area in the local caches while the unified miss handler manages all miss-related state and storage, improving area efficiency while maintaining manageable complexity through centralization.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS9323679B2System, method, and computer program product for managing cache miss requests
Publication Date: 2016.04.26 NVIDIA CORP
  • US9323679B2 patent drawing
  • US9323679B2 patent drawing
  • US9323679B2 patent drawing

AI summary

A system, method, and computer program product are provided for managing miss requests. In use, a miss request is received at a unified miss handler from one of a plurality of distributed local caches. Additionally, the miss request is managed, utilizing the unified miss handler.