Unified Integer Carry-less Modular Multiplier Circuit
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Solution Overview
Problem
Current software implementations of the Poly1305 algorithm, such as in ChaCha20/Poly1305, face performance limitations due to the need for 131×128-bit multiplication followed by reduction, while dedicated hardware accelerators for non-AES-GCM AEAD algorithms increase costs and design complexities.
Innovation Solution
A unified integer and carry-less modular multiplier circuit that can operate in multiple modes, including integer and carry-less modes, accelerates both AES-GCM and ChaCha20/Poly1305 by reconfiguring and reusing the multiplier, and employs an optimized Barrett reduction for efficient residue calculation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a dedicated hardware accelerator is used for non-AES-GCM AEAD algorithms, then the processing speed and performance are improved, but the device complexity and design complexity increase
Solution Approach 1:
The patent implements a unified multiplier circuit that can perform both integer multiplication and carry-less multiplication by reconfiguring its operation based on a control signal. This single multi-functional unit replaces what would traditionally require separate dedicated hardware accelerators for different AEAD algorithms, thereby improving processing speed while avoiding increased device complexity
Solution Approach 2:
The multiplier circuit incorporates dynamic reconfiguration capability where the same hardware can switch between different multiplication modes (integer and carry-less) based on the algorithm being executed. This dynamic adaptability allows the circuit to optimize performance for different algorithms without requiring static dedicated hardware for each algorithm type
2Productivity
If separate multipliers are used for different algorithms, then the algorithm-specific performance is optimized, but the area overhead and device complexity increase
Solution Approach 1:
The unified multiplier circuit performs both integer multiplication (for Poly1305) and carry-less multiplication (for AES-GCM) using the same hardware resources. By making the multiplier universal and capable of operating in different modes through reconfiguration, the patent eliminates the need for separate dedicated multiplier circuits for each algorithm, thereby reducing area overhead while maintaining algorithm-specific performance optimization
Solution Approach 2:
The patent merges the functionality of multiple algorithm-specific multipliers into a single unified multiplier circuit. By combining integer multiplication and carry-less multiplication capabilities in one hardware unit that can be reconfigured based on the algorithm requirements, the design reduces the total silicon area required while preserving the performance benefits of algorithm-optimized multiplication
Data Source
AI summary
In one embodiment, a processor comprises a multiplier circuit to operate in an integer multiplication mode responsive to a first value of a configuration parameter; and operate in a carry-less multiplication mode responsive to a second value of the configuration parameter.