Unified Non-Volatile Memory Dynamic Refresh Rate Control
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Solution Overview
Problem
Conventional electronic apparatuses with separate volatile and non-volatile memories face challenges in balancing access speed and battery life due to high power consumption and complex algorithms required to extend memory endurance.
Innovation Solution
A unified non-volatile memory system comprising a first memory section as ROM and a second memory section as RAM, where the control unit adjusts the refresh rate of the RAM based on access times to enhance memory endurance through simplified methods.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If volatile memory is used to temporarily store data to speed up access operation, then access speed is improved, but power consumption increases and battery life decreases
Solution Approach 1:
The patent merges volatile memory and non-volatile memory into a unified memory system where the same physical memory structure serves both volatile and non-volatile functions. This eliminates the need for separate memory components and reduces overall power consumption while maintaining access speed performance.
Solution Approach 2:
The patent implements dynamic refresh rate adjustment for the unified memory based on access frequency. When memory is frequently accessed, refresh operations are performed more often to maintain volatile-like performance. When access frequency is low, refresh rate is reduced to conserve power, enabling the memory to adapt its behavior dynamically.
2Ease of manufacture
If non-volatile memory is used as main storage to reduce cost, then cost is reduced, but access speed decreases
Solution Approach 1:
The patent combines non-volatile memory with volatile memory functionality in a unified structure. The non-volatile memory serves as the main storage providing cost benefits, while volatile memory is used only when necessary for high-speed access, optimizing both cost and performance.
Solution Approach 2:
The system dynamically adjusts the refresh rate of the unified memory based on access frequency. When high access speed is needed, the refresh rate is increased to provide volatile-like performance. When access speed requirements are lower, the refresh rate is reduced to maintain non-volatile memory characteristics, optimizing the trade-off between speed and cost.
3Speed
If DRAM is used for volatile memory to achieve high access speed, then access speed is improved, but refresh operations increase power consumption
Solution Approach 1:
The patent merges DRAM and non-volatile memory into a unified memory system that eliminates the need for continuous refresh operations characteristic of traditional DRAM. The unified memory only performs refresh operations when data needs to be maintained in volatile state, significantly reducing unnecessary power consumption.
Solution Approach 2:
The patent implements dynamic refresh rate adjustment based on actual access patterns. Instead of continuous refresh operations required by conventional DRAM, the unified memory performs refresh operations only when needed, adapting the refresh frequency to match the actual volatile memory usage requirements and minimizing power loss.
4Reliability
If ECC error correcting or access time monitoring is applied to extend memory endurance, then memory endurance is improved, but algorithm complexity increases
Solution Approach 1:
The patent merges error correction and endurance management functions into the unified memory structure itself, eliminating the need for separate complex ECC algorithms and access time monitoring systems. The unified memory inherently provides error correction capabilities through its design, simplifying the overall system.
Data Source
AI summary
An electronic apparatus comprising a unified non-volatile memory and a control unit is disclosed. The unified non-volatile memory comprises a first memory section, served as a read only memory; and a second memory section, served as a random access memory. The control unit controls the unified non-volatile memory. The first memory section further comprises: a first area for the first memory section; and a second area for the first memory section. The control unit adjusts a refresh rate of the second memory section according to a number of access times of the second memory section.