Unified Packet Buffer Memory Allocation for Network Switches
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Solution Overview
Problem
High-speed packet networks face buffer overflow issues due to delays in flow-control messages, leading to packet drops, and existing solutions limit flexibility in responding to varying network traffic patterns and system requirements by separating headroom and shared buffer memories.
Innovation Solution
A single memory array is used for both headroom and shared buffer spaces, with control logic dynamically allocating memory and tracking packet occupancy to apply flow-control operations, allowing direct transfer of packets from headroom to egress ports without copying, thereby simplifying queue handling and enhancing flexibility in memory allocation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate headroom and shared buffer memories are used, then buffer overflow protection is provided, but device complexity increases and flexibility decreases
Solution Approach 1:
The patent merges separate headroom memory and shared buffer memory into a single unified memory structure. This single memory serves both functions: it provides headroom protection against buffer overflow while also acting as the shared buffer for packet data. The merging eliminates the need for separate memory allocations and complex management logic, thereby reducing device complexity while maintaining reliability.
Solution Approach 2:
The single memory structure is designed to perform multiple functions simultaneously. It acts as both the headroom buffer for flow control operations and the shared buffer for packet data storage and transmission. This multi-functionality approach allows the same memory resource to serve different purposes, reducing overall memory requirements and simplifying the system architecture.
2Device complexity
If static buffer allocation is used, then memory management is simplified, but adaptability to varying traffic patterns decreases
Solution Approach 1:
The patent implements dynamic buffer allocation within the single memory structure. Instead of static allocation, the buffer space is dynamically adjusted based on real-time traffic conditions, queue lengths, and flow control requirements. This allows the system to adapt to varying traffic patterns while maintaining simplified memory management through a unified allocation mechanism.
Solution Approach 2:
The system changes buffer allocation parameters dynamically based on network conditions. The single memory structure allows flexible adjustment of buffer sizes, thresholds, and allocation ratios without requiring complex reconfiguration of separate memory blocks. This parameter flexibility enables adaptation to different traffic patterns while keeping management logic relatively simple.
3Stability of the object's composition
If copying packets between headroom and shared buffer is required, then memory isolation is maintained, but processing time increases
Solution Approach 1:
By merging headroom and shared buffer into a single memory structure, the patent eliminates the need for packet copying between separate memory regions. Packets can be directly allocated and managed within the unified memory space, removing the copy operation entirely. This maintains logical memory isolation through software management while achieving physical efficiency.
Solution Approach 2:
The patent extracts the unnecessary copying operation from the packet processing pipeline. By redesigning the memory architecture to eliminate separate headroom and buffer regions, the system removes the copy step that previously existed between these regions, thereby reducing processing time without compromising memory management integrity.
Data Source
AI summary
Communication apparatus includes multiple ports configured to serve as ingress ports and egress ports for connection to a packet data network. A single memory array is coupled to the ports and configured to contain both a respective headroom allocation for each ingress port and a shared buffer holding data packets for transmission in multiple queues via the egress ports. Control logic is configured to adjustably allocate to each ingress port a respective volume of memory within the single memory array to serve as the respective headroom allocation, and to queue the data packets in the multiple queues in the single memory array for transmission through the egress ports.