Unified Page Table for Independent CPU and DMA Access Control
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Solution Overview
Problem
Existing memory management technologies face challenges such as substantial memory overhead, software complexity, and performance overhead, particularly in secure address translation services and direct I/O operations.
Innovation Solution
The proposed solution involves extensions to the input/output memory management unit (IOMMU) and virtualization technology, which allow for independent control of central processor unit (CPU) and direct memory access (DMA) read/write permissions, enabling page-specific DMA prevention and transparent page-migration across CPU and I/O devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate page tables are maintained for CPU and I/O devices, then security against DMA attacks is improved, but device complexity and memory overhead increase
Solution Approach 1:
The patent merges CPU page tables and I/O page tables into a single unified page table structure. The IOMMU can selectively access appropriate page table entries within this unified structure based on whether the access is from a CPU or I/O device, eliminating the need for separate page tables while maintaining security boundaries through controlled access paths.
Solution Approach 2:
The unified page table structure serves multiple functions: it handles both CPU virtual address translations and I/O device address translations, and supports both pinned and non-pinned memory regions. The same page table infrastructure is used for different access types through configuration bits and selective access paths.
2Reliability
If address translation services are implemented with separate page tables, then security is improved, but memory overhead increases
Solution Approach 1:
The patent combines multiple page table structures into a single unified page table that serves both CPU and I/O devices. This consolidation eliminates redundant page table entries and reduces the total memory required for address translation structures while maintaining separate security boundaries through controlled access paths and configuration bits.
3Adaptability or versatility
If non-pinned memory regions are supported, then adaptability is improved, but performance overhead increases due to additional translation steps
Solution Approach 1:
The system performs preliminary actions by pre-establishing the unified page table structure with all necessary translation entries before runtime operations. The IOMMU is pre-configured with access paths to both pinned and non-pinned memory regions, allowing it to handle both types of accesses efficiently without requiring runtime page table switching or additional translation overhead.
Data Source
AI summary
An embodiment of an integrated circuit comprises circuitry to share page tables associated with a page between a processor memory management unit (MMU) and an input/output memory management unit (IOMMU), store a page table entry in the memory associated with the page, and separately control access to the page from a processor and from a direct memory access (DMA) request based on one or more fields of the stored page table entry. Other embodiments are disclosed and claimed.