Unified Page Table Walker Cache for TLB Translation
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Solution Overview
Problem
Managing multi-level page tables in computing systems can consume a significant amount of time, particularly during translation lookaside buffer misses, and existing approaches often restrict the dynamic allocation of entries to page table levels.
Innovation Solution
Implementing a hierarchical page table system with a memory management unit (MMU) that includes a first cache for final mappings, a page table walker, and a second cache for intermediate results, allowing for efficient comparison and invalidation of entries based on match criteria associated with each level, and utilizing a physical memory interface to access data referenced by physical addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a multi-level page table system is used to manage virtual memory translations, then the flexibility and scalability of memory address mapping is improved, but the time required for address translation increases significantly
Solution Approach 1:
The patent pre-calculates and stores intermediate translation results from multi-level page tables in the TLB entries. When a virtual address is translated, the system performs preliminary actions by fetching multiple levels of page table entries simultaneously and computing intermediate results in advance, so that subsequent translations can reuse these pre-computed values without重新 traversing the entire multi-level page table structure.
Solution Approach 2:
The patent dynamically allocates TLB entry resources to store different types of translation information based on the multi-level page table structure. The TLB is configured to adaptively store both final physical address mappings and intermediate translation results, with entry formats that can be dynamically selected based on the page table level being accessed, optimizing the balance between translation speed and mapping flexibility.
2Device complexity
If traditional TLB structures are used for caching page table entries, then the implementation is simple, but the ability to efficiently manage multi-level page table translations is limited
Solution Approach 1:
The patent enhances the TLB structure to perform multiple functions: it can store both traditional final physical address mappings and new intermediate translation results from multi-level page tables. The TLB entry format is designed to be universal, supporting different page table levels (first level, second level, third level intermediates) within the same cache structure, allowing a single TLB to efficiently handle translations at any level of the page table hierarchy without requiring separate cache structures.
3Speed
If intermediate results from page table traversal are cached, then translation speed is improved, but the complexity of managing and invalidating cache entries increases
Solution Approach 1:
The patent implements a feedback mechanism where the TLB tagging system includes information about the page table level associated with each cached entry. When an address translation is performed, the system provides feedback by comparing the accessed virtual address against cached entries with appropriate level tags, enabling selective invalidation or updating of only those entries that are relevant to the current translation operation, thus managing complexity through intelligent feedback-based selection.
Data Source
AI summary
A core executes memory instructions. A memory management unit (MMU) coupled to the core includes a first cache that stores a plurality of final mappings of a hierarchical page table, a page table walker that traverses levels of the page table to provide intermediate results associated with respective levels for determining the final mappings, and a second cache that stores a limited number of intermediate results provided by the page table walker. The MMU compares a portion of the first virtual address to portions of entries in the second cache, in response to a request from the core to invalidate a first virtual address, based on a match criterion that depends on the level associated with each intermediate result stored in an entry in the second cache, and removes any entries in the second cache that satisfy the match criterion.