Unified PCM Network for Flexible FPGA Tile Reallocation
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Solution Overview
Problem
Programmable logic devices face challenges in efficiently communicating signals to and from their programmable logic regions due to architectural limitations, hindering flexible operation and application switching.
Innovation Solution
A programmable device with a unified programmable computational memory (PCM) and configuration network that allows configuration data and transactional data to be transmitted through the network, enabling dynamic allocation of PCM tiles between computation and memory regions and supporting flexible operation and application switching.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a traditional programmable logic device architecture is used with separate configuration and data paths, then configuration can be achieved, but signal communication efficiency and flexibility are hindered
Solution Approach 1:
The patent merges the configuration network and data transmission network into a single unified PCM network. Configuration data and transactional data share the same physical network infrastructure, eliminating the need for separate configuration paths and data paths. This consolidation improves signal communication efficiency while reducing overall architectural complexity through resource sharing.
Solution Approach 2:
The unified PCM network serves multiple functions: it transmits both configuration data during programming and transactional data during operation. The network infrastructure is designed to be universal, handling different types of data traffic through the same physical channels, thereby improving productivity without requiring additional dedicated pathways.
2Adaptability or versatility
If fixed functional regions are used in programmable logic devices, then manufacturing is simplified, but adaptability for different applications is reduced
Solution Approach 1:
The patent implements dynamic allocation of PCM tiles between computation and memory regions based on application requirements. The fabric architecture allows functional regions to be reconfigured and reassigned during operation, enabling the system to adapt to different applications without requiring physical remanufacturing. This dynamic flexibility is achieved through software-controlled allocation rather than fixed hardware boundaries.
Solution Approach 2:
The system changes operational parameters by reconfiguring the function of PCM tiles through configuration data. Rather than manufacturing different fixed functional regions for different applications, the patent modifies the logical function of existing hardware resources through parameter changes in the configuration memory, maintaining manufacturing simplicity while achieving high adaptability.
3Productivity
If separate configuration and operational memory regions are used, then data storage is organized, but resource utilization efficiency decreases
Solution Approach 1:
The patent combines configuration memory and operational memory into a single unified PCM memory structure. The same physical memory resources serve both configuration storage and operational data storage functions, improving resource utilization efficiency by allowing dynamic allocation of memory capacity between these two purposes based on real-time needs, rather than dedicating fixed portions to each function.
Solution Approach 2:
The memory architecture enables dynamic allocation where PCM tiles can be assigned to either configuration or operational memory roles depending on application requirements. This dynamic memory management allows the system to optimize resource utilization for different workloads without requiring separate fixed memory regions, achieving high productivity while managing complexity through unified control logic.
Data Source
AI summary
Examples generally relate a programmable device having a unified programmable computational memory (PCM) and configuration network. In an example, a programmable device includes a die that includes a PCM integrated circuit having a PCM tile. The PCM tile includes a configuration memory (CM) and combinational logic (CL). The CM is capable of storing configuration data received via a node in the PCM tile. The CL is configured to receive internal control signal(s) and first and second input signals and to output a result signal. The CL is capable of outputting the result signal resulting from a logic function that is responsive to the internal control signal(s) and a signal of a group of signals including the first and second input signals. The CL is configured to receive the first input signal via the node in the PCM tile.