Unified Pointer Processor for SONET Overhead Labeling
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Solution Overview
Problem
Conventional Sonet/SDH framing systems require multiple clock domains and separate logic elements for each channel, leading to inefficiency and increased complexity due to the need for separate high and low order pointer processors, which are mutually exclusive in operation.
Innovation Solution
Implementing a system that uses a common clock frequency across multiple interfaces by deleting unnecessary overhead bytes and combining high and low order pointer processors into a single block, with a labeler to manage and process both types of pointers efficiently, allowing for shared logic elements and reduced logic requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate high order and low order pointer processors are employed, then each function can be performed, but a large number of logic elements are required and logic elements cannot be shared between channels
Solution Approach 1:
The patent combines separate high order and low order pointer processors into a single unified pointer processor that can handle both types of pointer processing. This consolidation allows logic elements to be shared between channels and reduces the total number of logic elements required, while maintaining the ability to perform both high order and low order pointer processing functions.
Solution Approach 2:
The unified pointer processor is designed to be multi-functional, capable of performing both high order pointer processing and low order pointer processing within the same logic block. This universal processor can be shared across multiple channels, eliminating the need for dedicated separate processors for each channel and reducing overall device complexity.
2Reliability
If separate clock domains are used for each channel, then data integrity is maintained, but logic elements cannot be shared and device complexity increases
Solution Approach 1:
The patent merges multiple channel-specific clock domains into a single shared clock domain that serves all channels. The unified pointer processor operates within this single clock domain and can be time-shared or parallelized to handle multiple channels, thereby reducing the number of clock domains while maintaining data integrity through proper synchronization and buffering mechanisms.
3Adaptability or versatility
If multiple clock domains are implemented, then frequency offsets can be accommodated, but the number of logical blocks and logic elements increases significantly
Solution Approach 1:
The patent accommodates frequency offsets by changing the operational parameters of the unified pointer processor rather than creating separate clock domains. The processor can dynamically adjust its operating frequency and timing parameters to handle different channel frequencies within a single clock domain, reducing the need for multiple dedicated logical blocks while maintaining adaptability to frequency variations.
Data Source
AI summary
A method and system for providing single stage pointer and overhead processing is disclosed. In accordance with one embodiment of the invention, data including bytes of each of multiple types of overhead data is received at a logical element of a communications network. The logical element includes a labeler to label the bytes of each of the multiple types of overhead data and a pointer processor to read the labeled bytes and perform specific operations corresponding to the label, wherein the bytes of at least one type of overhead data are labeled based on feedback provided by the pointer processor to the labeler.