Unified Power Map for Low Power IC Anomaly Detection

The patent introduces an intermediary system that translates both HDL descriptions and power specification descriptions into a unified power map representation. This power map serves as a mediator that integrates information from both separate descriptions, enabling systematic anomaly detection without requiring direct coupling of the original separate formats. The intermediary translation process maintains design flexibility while enabling comprehensive debugging through unified visualization and analysis.

The patent merges the separate HDL description and power specification description into a unified power map that captures both functional and power-related information. This merging process combines elements from both separate formats into a single integrated representation, enabling comprehensive anomaly detection that considers interactions between functional behavior and power management. The unified power map maintains the modularity benefits of separate descriptions while providing integrated anomaly detection capability.

The patent performs preliminary translation of both HDL and power specification descriptions into a unified power map representation before the actual debugging process. This preliminary action creates an integrated view that anticipates potential anomalies by establishing relationships between functional and power behaviors in advance. When debugging is needed, the pre-established power map enables rapid anomaly detection without requiring time-consuming manual correlation of separate file formats, thus reducing overall debugging time while maintaining format independence.