Unified Pre-Charge Operation for Nonvolatile Memory Speed
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Solution Overview
Problem
Current nonvolatile semiconductor memory devices face inefficiencies in programming and reading operations due to bit line coupling and the need for separate pre-charging methods for verification and read operations, which affect performance and speed.
Innovation Solution
A nonvolatile memory device with a unified pre-charge operation for both verification and read operations, where all bit lines are pre-charged simultaneously, and a control logic that manages programming and verification across multiple memory cell groups, reducing bit line coupling and improving operational speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If separate pre-charging methods are used for verification and read operations, then sensing accuracy is maintained, but operational speed and efficiency deteriorate
Solution Approach 1:
The patent merges the pre-charging operations for verification and read operations into a single unified process. The control logic unit coordinates both operations to share the same pre-charging sequence, eliminating the need for separate pre-charging methods while maintaining sensing accuracy and improving operational speed.
2Loss of time
If bit lines are pre-charged separately for verification and read operations, then sensing precision is preserved, but time consumption increases
Solution Approach 1:
The patent implements preliminary action by performing a single pre-charging operation that prepares both verification and read bit lines in advance. The control logic unit configures the pre-charging sequence to accommodate both operations simultaneously, reducing time consumption while preserving sensing precision through proper timing control.
3Productivity
If multiple separate pre-charge operations are performed, then operational reliability is maintained, but program performance deteriorates
Solution Approach 1:
The patent applies universality by designing a unified pre-charge operation that serves multiple functions: it prepares bit lines for both verification and read operations, and can accommodate different read modes (full page read and partial page read). This multi-functional approach improves program performance while maintaining operational reliability through consistent pre-charging protocols.
Data Source
AI summary
A nonvolatile memory device includes a first memory cell group connected to a first word line and a first bit line group, a second memory cell group connected to the first word line and a second bit line groups (BLGs), a control logic that performs first and second program operations on the first and second memory cell groups, respectively, performs a verification operation on the first memory cell group by pre-charging bit lines in the first and second BLGs at a same time to verify the first program operation, and a verification operation on the second memory cell group by pre-charging the bit lines in the first and second BLGs at a same time to verify the second program operation, and performs a read operation on at least one of the first and second memory cell groups by simultaneously pre-charging the bit lines in the first and second BLGs.