Unified Processor Register with Error Processing Circuit
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Solution Overview
Problem
The existing processor design, which includes both a work register and a general-purpose register, leads to increased area and power consumption due to the need for separate error handling and data management for pre-commit and post-commit data, potentially resulting in unnecessary system error information transmission and infinite loop processing.
Innovation Solution
A processor configuration that combines the work register and general-purpose register into a single storage unit, with an error processing circuit that adds error checking and correcting information to data, allowing for efficient error detection and correction, and preventing unnecessary system error transmission by distinguishing between pre-commit and post-commit data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If both work register and general purpose register are included in the processor, then error detection and correction capability is improved, but processor area and power consumption increase
Solution Approach 1:
The patent combines the work register and general purpose register into a single unified register structure. This merging eliminates the need for separate error handling circuits for each register type, thereby reducing processor area and power consumption while maintaining error detection and correction capabilities through a unified error processing circuit that manages both pre-commit and post-commit data
2Reliability
If both work register and general purpose register are included in the processor, then error detection and correction capability is improved, but power consumption increases
Solution Approach 1:
The patent merges the work register and general purpose register into one unified register, which consolidates the error handling functionality. This reduces the number of separate error detection and correction circuits needed, thereby lowering power consumption while maintaining comprehensive error protection for all register operations
3Reliability
If separate error handling is implemented for pre-commit and post-commit data, then error management is improved, but device complexity increases
Solution Approach 1:
The patent implements a unified error processing circuit that handles both pre-commit and post-commit data within a single integrated structure. This merging approach simplifies the overall processor architecture by eliminating the need for separate error handling paths, reducing device complexity while maintaining comprehensive error management capabilities
Solution Approach 2:
The unified error processing circuit is designed to perform multiple functions: it detects errors in both pre-commit and post-commit data, generates appropriate error signals, and coordinates with the unified register structure. This multi-functional design reduces the number of dedicated circuits needed, thereby simplifying the overall device complexity
Data Source
AI summary
A processor includes: an error checking and correcting information generating unit; a storage unit configured to store data to which error checking and correcting information and error uncorrectable information are added when an error is detected and configured to store data to which error checking and correcting information is added when an error is not detected; and a processing unit configured to read out all data which the storage unit stores and configured to check an error of each piece of read-out data based on error checking/correcting information added to each piece of all the read-out data when an arithmetic unit detects an error, and configured to correct data in which an error is detected based on error checking and correcting information when a correctable error is detected.