Unified RISC-V IDE for Heterogeneous Multi-Core Debug
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Solution Overview
Problem
Current SoC design with heterogeneous multi-core architectures faces challenges in using separate toolsets for each core, limiting SoC-wide debug and verification, and lacking multi-core support within a single toolchain, especially when integrating processor architectures from different vendors like ARM, ARC, MIPS, and RISC-V.
Innovation Solution
RiscFree is an Eclipse-based Integrated Development Environment (IDE) that provides a single, fully-functional toolchain for developing, debugging, and tracing across ARM, ARC, MIPS, and RISC-V cores, enabling simultaneous multi-core support and debug capabilities within a unified platform.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate toolsets are used for each core in heterogeneous multi-core SoC, then each core can be developed independently, but SoC-wide debug and verification becomes impossible and multi-core support within a single toolchain is not available
Solution Approach 1:
The patent implements a universal toolchain that can debug and verify multiple heterogeneous processor cores (ARM, RISC-V, ARC, MIPS) within a single integrated environment. The debug probe and software development tools are designed to support multiple ISAs and architectures simultaneously, eliminating the need for separate vendor-specific toolsets and enabling SoC-wide debug and verification across all cores.
2Productivity
If multiple vendor processor architectures are integrated onto a single SoC, then performance and feature requirements are met, but engineers must use separate toolsets for each core
Solution Approach 1:
The debug probe and development tools are designed with universal support for multiple processor architectures including ARM, RISC-V, ARC, and MIPS. This allows engineers to develop, debug, and verify software across all heterogeneous cores using a single toolchain, greatly simplifying the development process while maintaining the ability to execute subsystems in parallel on different core types.
3Reliability
If vendor-specific toolsets are used for each processor architecture, then each toolset is optimized for its specific core, but simultaneous multi-core debug of different architectures is not possible
Solution Approach 1:
The patent describes a unified toolchain implementation that maintains optimized support for each specific processor architecture (ARM, RISC-V, ARC, MIPS) while integrating them all into a single debug probe and development environment. This universal toolchain enables simultaneous multi-core debugging across different architectures without requiring separate vendor-specific toolsets, thus maintaining reliability while reducing complexity.
Data Source
AI summary
System unique artificial intelligence in a multi-core heterogeneous embedded system. a software-based invention to solve the problem of allowing simultaneous, multi-core, heterogeneous embedded debug in an efficient and abstracted manner. Ashling Microsystems is developing a system to support multiple heterogeneous processors. Starting address: The software was developed to solve the technical problems of simultaneous transmission, multi-mode, integration and independence from hardware protocols. The hardware and software are designed to efficiently, instantly and seamlessly add (encode and decode) multiple different simultaneous program instructions within a single stream, thereby increasing the amount of bandwidth.