Dynamic Power Reduction in Unified Scheduler via Selective Precharge
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Solution Overview
Problem
Conventional schedulers experience significant power waste due to unnecessary precharging and evaluation of grant lines, as many instructions are precharged in the precharge phase only to be discharged in the evaluation phase, leading to inefficient power consumption.
Innovation Solution
Implementing a scheduler with a validity block and selective precharge mechanism, where grant lines are only precharged for valid instructions and evaluation is limited to ready instructions, reducing unnecessary power usage by avoiding precharging and evaluation of non-ready instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all grant lines are precharged in the precharge phase, then all instructions have the opportunity to be evaluated, but power is wasted on precharging and evaluating non-ready instructions
Solution Approach 1:
The patent applies preliminary action by precharging only those grant lines corresponding to ready instructions before the evaluation phase. The wakeup block identifies ready instructions in advance, and the picker block selectively precharges only the necessary grant lines, avoiding waste on non-ready instructions while ensuring all ready instructions are properly evaluated
Solution Approach 2:
The patent implements local quality by differentiating the precharge treatment of grant lines based on instruction readiness status. Ready instructions receive precharge treatment while non-ready instructions do not, creating a localized optimization where resources are allocated only where needed rather than uniformly across all instructions
2Productivity
If the scheduler evaluates all precharged grant lines, then all instructions are considered for execution, but power is wasted evaluating instructions that cannot be executed
Solution Approach 1:
The patent uses preliminary action by having the wakeup block identify ready instructions before the evaluation phase begins. This advance identification allows the picker block to restrict evaluation to only those instructions that are ready for execution, eliminating wasted evaluation cycles on non-ready instructions while maintaining complete coverage of all executable instructions
Solution Approach 2:
The patent applies partial action by evaluating only the subset of instructions that are ready for execution, rather than evaluating all instructions in the instruction silo. This partial evaluation approach reduces power consumption by avoiding unnecessary evaluation of non-ready instructions while still achieving complete instruction throughput for all ready instructions
Data Source
AI summary
A scheduler and method for dynamic power reduction, e.g., in a processor core, is proposed. In conventional processor cores for example, the scheduler precharges grant lines of many instructions only to discharge a great majority of the precharged lines in one cycle. To reduce power consumption, selective precharge and/or selective evaluation are proposed. In the selective precharge, the grant lines of instructions that will evaluate to false (e.g., invalid instructions) are not precharged in a cycle. In the selective evaluation, among the precharged instructions, instructions that are not ready are not evaluated in the same cycle. In this way, power consumption is reduced by avoiding unnecessary precharge and discharge.