Unified Set Indexing for Multi-Level Cache Migration

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Solution Overview

Problem

In multi-level cache hierarchies, the conventional approach of using different numbers of sets and indexing schemes for first and second-level set-associative caches can lead to performance issues, particularly when cache entries are migrated between levels, as it requires additional updates and increases latency.

Innovation Solution

Aligning the number of sets and using a common indexing scheme for both first and second-level set-associative caches simplifies the migration process by ensuring that the set index is the same for both levels, reducing the need for unnecessary updates and improving access performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If different numbers of sets and indexing schemes are used for first and second-level caches, then cache capacity and flexibility are improved, but migration complexity and latency increase

Engineering Contradiction:
Improvecache capacityVSAvoidmigration complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent applies universality by making the set indexing scheme common to both first-level and second-level caches. The indexing circuitry uses the same indexing logic for both cache levels, allowing the system to handle both small and large cache capacities while maintaining a unified access pattern. This resolves the contradiction by enabling different cache capacities without requiring different indexing schemes, thus reducing migration complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Adaptability or versatility

If different indexing schemes are used for first and second-level caches, then adaptability is improved, but access latency increases

Engineering Contradiction:
Improveindexing flexibilityVSAvoidaccess latency
Core Design Contradiction:
Adaptability or versatilityVSLoss of time

Solution Approach 1:

The patent applies homogeneity by using the same indexing scheme for both first-level and second-level caches. The indexing circuitry generates set indices using identical logic for both cache levels, creating a homogeneous access pattern. This reduces access latency by eliminating the need to adapt to different indexing schemes while maintaining adaptability through the unified approach that works for both cache sizes.

Inventive Principle:
Principle #33Homogeneity

3Productivity

If the number of sets is aligned between first and second-level caches, then migration overhead is reduced, but cache capacity flexibility decreases

Engineering Contradiction:
Improvemigration efficiencyVSAvoidcapacity flexibility
Core Design Contradiction:
ProductivityVSAdaptability or versatility

Solution Approach 1:

The patent resolves this contradiction by changing the dimension of cache organization. Instead of varying the number of sets (one dimension), the system aligns the number of sets and varies the associativity (another dimension - number of ways per set). This allows both cache levels to have the same number of sets for efficient migration while achieving different total capacities through different associativity values, thus maintaining capacity flexibility without sacrificing migration efficiency.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11455253B2Set indexing for first-level and second-level set-associative cache
Publication Date: 2022.09.27 ARM LTD
  • US11455253B2 patent drawing
  • US11455253B2 patent drawing
  • US11455253B2 patent drawing

AI summary

An apparatus comprises first-level and second-level set-associative caches each comprising the same number of sets of cache entries. Indexing circuitry generates, based on a lookup address, a set index identifying which set of the first-level set-associative cache or the second-level set-associative cache is a selected set of cache entries to be looked up for information associated with the lookup address. The indexing circuitry generates the set index using an indexing scheme which maps the lookup address to the same set index for both the first-level set-associative cache and the second-level set-associative cache. This can make migration of cached information between the cache levels more efficient, which can be particularly useful for caches with high access frequency, such as branch target buffers for a branch predictor.