Unified Symbolic Store Address Buffer for Parallel Processor
Solution Overview
Problem
Non-blocking processor microarchitectures require significant chip real estate and power consumption due to the need for per lane store address buffers and content addressable memory logic to manage store operations and memory ordering conflicts.
Innovation Solution
A processor architecture that generates symbolic addresses for store operations, using a unified symbolic store address buffer to reduce area and power consumption, allowing for speculative dispatch and execution of load instructions while maintaining memory ordering consistency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If per lane store address buffers and content addressable memory logic are used to manage store operations and memory ordering conflicts, then memory ordering consistency is maintained, but chip area and power consumption increase significantly
Solution Approach 1:
The patent merges per-lane store address buffers into a single unified store address buffer shared across all execution lanes. Instead of maintaining separate buffers for each lane, the system combines them into one centralized structure, reducing the total chip area required while still managing memory ordering for all lanes effectively.
Solution Approach 2:
The unified store address buffer serves multiple execution lanes simultaneously, making it a universal resource. This single buffer structure handles store address management for all lanes, eliminating the need for dedicated per-lane buffers and reducing overall hardware footprint while maintaining functionality across all lanes.
2Reliability
If per lane store address buffers and content addressable memory logic are used to manage store operations and memory ordering conflicts, then memory ordering consistency is maintained, but power consumption increases significantly
Solution Approach 1:
By merging per-lane store address buffers into a unified buffer, the patent reduces the number of separate memory structures that need to be maintained and accessed. This consolidation reduces the total power consumption associated with buffer management, address comparison logic, and control circuitry across all execution lanes.
3Reliability
If store address is generated per lane at STA dispatch and stored in per lane store address buffer, then memory ordering is enforced, but scheduling logic complexity and chip area increase
Solution Approach 1:
The patent combines multiple per-lane store address buffers into a single unified buffer structure. This merging simplifies the scheduling logic by eliminating the need for separate buffer management, address comparison, and conflict resolution logic for each lane, while still maintaining proper memory ordering through the unified structure.
Data Source
Figure 1A
Figure 1B
Figure 2A~2B
AI summary
In one embodiment, an apparatus includes: a plurality of execution lanes to perform parallel execution of instructions; and a unified symbolic store address buffer coupled to the plurality of execution lanes, the unified symbolic store address buffer comprising a plurality of entries each to store a symbolic store address for a store instruction to be executed by at least some of the plurality of execution lanes. Other embodiments are described and claimed.