Unified Tag Sliced Data Cache for Multi-Core Latency
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Solution Overview
Problem
In multi-core processors with cache memory, maintaining cache coherency and memory consistency while minimizing latency and maximizing throughput is challenging, particularly in shared last level cache (LLC) designs where latency and throughput are critical performance measures.
Innovation Solution
A cache memory architecture is implemented with a unified tag part and sliced data structure, where each data slice is physically local to one core and remote from others, biasing allocations towards the locally situated slice to reduce access latency, and a dispatch queue manages requests to ensure only one slice returns data to each core at a time, minimizing collisions and optimizing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a shared last level cache (LLC) is used in multi-core processors, then memory throughput is improved, but access latency increases due to shared access conflicts
Solution Approach 1:
The data part of the cache is segmented into N slices, each physically local to a specific core. This segmentation allows each core to access its local slice with low latency while the unified tag part maintains coherency across all cores, resolving the contradiction between shared throughput and individual access latency
Solution Approach 2:
Each data slice is positioned physically close to its corresponding core, creating local quality differences where nearby accesses are fast and remote accesses are slower. The allocation bias towards local slices ensures that each core predominantly accesses local data, minimizing latency while maintaining high throughput through the shared unified tag structure
2Reliability
If data is stored in a unified structure shared by all cores, then data coherency is maintained, but access latency increases due to remote access requirements
Solution Approach 1:
The cache is segmented into a unified tag part and sliced data parts. The unified tag part maintains data coherency information for all cores, while the data slices are physically distributed close to respective cores. This segmentation allows coherency to be maintained centrally while data access occurs locally, resolving the contradiction between coherency and access latency
Solution Approach 2:
The unified tag part acts as an intermediary that maintains coherency information for all cores. When a core needs data, it first checks the unified tag part to determine which data slice contains the data, then accesses the appropriate local slice. This intermediary structure enables both coherency maintenance and low-latency local access
3Productivity
If multiple data slices are accessed simultaneously by different cores, then throughput is improved, but collisions occur when multiple slices return data to the same core at the same time
Solution Approach 1:
The dispatch queue monitors which data slices are currently returning data and uses this feedback information to make intelligent dispatch decisions. When a core is receiving data from one slice, the dispatch queue feedback prevents dispatching requests to other slices that would also return data to the same core, eliminating collisions while maintaining high throughput through parallel operations on other cores
Data Source
AI summary
A cache memory is shared by N cores of a processor. The cache memory includes a unified tag part and a sliced data part partitioned into N data slices. Each data slice of the N data slices is physically local to a respective one of the N cores and physically remote from the other N-1 cores. For each core, the cache memory biases allocations caused by the core towards a physically local slice of the core. The cache memory may be arranged as a set-associative cache memory, and allocations may be based on a miss rate of a data slice and a number of M ways allocated to a core. A dispatch queue dispatches requests in a schedule fashion so that only one of the N data slices at a time returns data to each core.