Unified Test Bench for Semiconductor Equivalence Checking
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Solution Overview
Problem
Existing techniques for equivalence checking of semiconductor integrated circuits require separate test benches for different circuit descriptions, making it difficult to maintain equivalence judgment across various stages of operation composition due to differences in input/output access timing cycles.
Innovation Solution
A method that utilizes a test bench for equivalence checking by synchronizing the input/output access timing cycles between a sample model and a model to be verified through FIFO groups, allowing the same test bench to be used for both, thereby eliminating the need for manual modification and increasing efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate test benches are used for different circuit descriptions, then equivalence checking can be performed, but the complexity of the checking process increases and manual modification is required
Solution Approach 1:
The patent creates a unified test bench that can handle multiple circuit descriptions (input description and output description) with different input/output access timing cycles. By introducing FIFO groups as universal interface components, the same test bench structure serves multiple verification purposes without requiring separate configurations for each circuit description type.
Solution Approach 2:
FIFO groups are introduced as intermediary components between the test bench and circuit descriptions. These FIFO buffers mediate the timing differences between input and output descriptions, allowing the test bench to interface with circuits having different access timing cycles without requiring manual test bench modification.
2Adaptability or versatility
If manual modification of test benches is performed for each circuit description, then equivalence checking can be adapted, but the time and effort required increases significantly
Solution Approach 1:
The checking process is automated to perform self-service by automatically generating and configuring the unified test bench. The system automatically determines the appropriate FIFO group configurations based on the circuit descriptions being verified, eliminating the need for manual test bench modification while maintaining adaptability to different circuit types.
Solution Approach 2:
The patent pre-configures the test bench with FIFO groups before actual equivalence checking begins. By establishing the unified test bench structure in advance with appropriate buffering mechanisms, the system prepares for handling various circuit descriptions without requiring time-consuming modifications during the verification process.
3Productivity
If FIFO groups are introduced to synchronize timing cycles, then the same test bench can be used, but the device complexity increases
Solution Approach 1:
The test bench is segmented into functional modules, with FIFO groups separated as distinct interface components. This segmentation allows the core test bench logic to remain simple while timing synchronization is handled by dedicated FIFO modules, making the overall system more manageable despite the added complexity.
Data Source
AI summary
To provide a checking method that utilizes a test bench for a circuit model, which will serve as a fundamental for equivalence checking of a circuit to be newly developed for the fundamental circuit model. In order to check the equivalence of a model to be verified using a sample model a circuit of which has been described in a predetermined language and a test vector generation model for the sample model, a process for writing an output from the sample model test vector generation model into an input FIFO group for each signal of the sample model with the same timing as that of the sample model while the sample model is inputting/outputting a signal from/to the sample model test vector generation model with cycle accuracy and a process for reading data from the input FIFO group with the same operation timing as that of the model to be verified and outputting the data to the model to be verified are carried out. The output of the sample model and the output of the model to be verified are written into an output FIFO pair group for each corresponding signal name and coincidence judgment is carried out for a pair output for each written signal name.