Unified Test Power Isolation Circuit for Multi-Domain ICs
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Solution Overview
Problem
In large digital integrated circuits with multiple power domains, the insertion of test wrapper cells and power isolation cells on I/O paths leads to increased logic and area overhead, power consumption, and timing delays, complicating the physical design and performance optimization.
Innovation Solution
A power isolation circuit and method that combines test wrapper cells and power isolation logic, using a power control unit to control isolation cells based on DFT internal core test mode and clamp control signals, reducing the number of multiplexors and cells required, thereby minimizing delay and area overhead while maintaining functionality in both test and low-power modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If test wrapper cells and power isolation cells are inserted on I/O paths, then test mode isolation and power management are achieved, but logic and area overhead, power consumption, and timing delays increase
Solution Approach 1:
The patent combines test wrapper cells and power isolation cells into a unified structure where the test wrapper cell includes both test functionality and power isolation functionality. This merging eliminates the need for separate power isolation cells, reducing logic overhead and area while maintaining both test mode isolation and power management capabilities
Solution Approach 2:
The test wrapper cell is designed to serve multiple functions: it provides test mode isolation, power isolation, and power management simultaneously. By making the test wrapper cell universal, the patent eliminates redundant components and reduces overall device complexity while achieving multiple objectives with a single structure
2Reliability
If test wrapper cells and power isolation cells are inserted on I/O paths, then test mode isolation and power management are achieved, but power consumption increases
Solution Approach 1:
By merging power isolation functionality into the test wrapper cell, the patent eliminates redundant power isolation cells and their associated power consumption. The unified structure shares control logic and circuitry, reducing overall power consumption while maintaining effective power isolation between domains
3Reliability
If test wrapper cells and power isolation cells are inserted on I/O paths, then test mode isolation and power management are achieved, but timing delays increase
Solution Approach 1:
The patent merges test and power isolation cells into a single unified structure, reducing the number of sequential logic stages and physical components in the I/O path. This consolidation shortens signal propagation delays and improves timing performance while maintaining test mode isolation functionality
4Adaptability or versatility
If separate test wrapper cells and power cells are inserted on the same I/O paths, then test and power functions are provided, but physical design congestion and routing complexity increase
Solution Approach 1:
The patent combines test wrapper cells and power isolation cells into a single integrated structure, eliminating the need for separate routing paths and reducing physical design congestion. The unified cell requires fewer routing connections and simplifies placement and routing during physical design while maintaining both test and power management functionality
Data Source
AI summary
Embodiments include a power isolation circuit. The power isolation circuit includes a logic block, a wrapper cell, an isolation cell, a test control unit, and/or a power control unit. The power control unit is coupled to the isolation cell and configured to receive a DFT internal core test mode control signal and a clamp control signal, and control the isolation cell dependent on the DFT internal core test mode control signal and the clamp control signal. Also disclosed is a multi-power domain multi-power isolation system, which includes a first power domain and a second power domain. The first power domain includes a logic block, wrapper cells, isolation cells, and a power control unit. The second power domain includes a logic block, wrapper cells, and level-shifter cells. The power control unit is coupled to the isolation cells. Additional power domains with similar characteristics can be included in the design.