Unified Timestamp Timer for Asymmetric Multi-Core Systems
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Solution Overview
Problem
In asymmetric multi-core systems, independent timers for different operating systems lack a common time base, making it challenging to maintain synchronized timing across multiple core domains without software programming of registers, which can lead to timing setting overrides.
Innovation Solution
A unified timestamp timer (TS Timer) in the primary domain is used as a base for secondary domains, with timer adjust circuits that adjust the TS Timer value to provide a unified OS timer, eliminating the need for software programming and ensuring all domains start with zero upon power-up.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If independent decoupled timers are used for each operating system in multi-core systems, then each OS can have its own timer, but a common time base between OSes is not provided
Solution Approach 1:
The patent merges multiple independent timer functions into a single unified timestamp timer circuit located in the primary domain. This single timer provides a common time base for all operating systems through timer adjust circuits that distribute and adapt the timestamp values to secondary domains, ensuring synchronized timing across heterogeneous OSes while maintaining their operational independence.
Solution Approach 2:
The timestamp timer circuit acts as an intermediary between the primary domain and secondary domains. It generates a unified timestamp that is then adjusted and distributed to secondary domains through timer adjust circuits, mediating the timing synchronization between different OSes without requiring direct independent timer hardware in each domain.
2Ease of operation
If software programming of timer registers is used to set timing values, then timing can be configured, but timing settings can be overridden
Solution Approach 1:
The timer adjust circuits automatically configure timing values through hardware-based adjustment mechanisms rather than requiring software programming. The circuits self-configure by receiving the timestamp from the primary domain and automatically adjusting it according to domain-specific requirements, eliminating the need for software intervention and preventing accidental or malicious overrides of timing settings.
Solution Approach 2:
The patent replaces software-based timer configuration (mechanical/system-level programming) with hardware-based automatic adjustment mechanisms. The timer adjust circuits use hardware logic to automatically configure and protect timing settings, substituting the vulnerable software registration system with a more reliable hardware-enforced configuration mechanism.
3Reliability
If a unified timestamp timer is used in the primary domain, then a common time base is provided, but timer values must be adjusted for secondary domains
Solution Approach 1:
The patent segments the timer functionality into two distinct components: a unified timestamp timer circuit in the primary domain that generates the common time base, and separate timer adjust circuits in secondary domains that adapt the timestamp values. This segmentation allows the system to maintain a simple unified timer while providing domain-specific timing adjustments through dedicated adjustment circuits.
Data Source
AI summary
An integrated circuit includes a first processing domain configured to run a first operating system and a second processing domain configured to run a second operating system that is different than the first operating system. The integrated circuit further includes a time stamp timer circuit in the first processing domain configured to provide a first time stamp value to the first processing domain and an adjusted second time stamp value to the second processing domain. The time stamp timer circuit includes a timer adjust circuit configured to synchronize the adjusted second time stamp value when a power up signal is received by the time stamp timer circuit from the second processing domain.