Unified TLB Lookup with Dynamic Page Size Priority

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Solution Overview

Problem

Existing address translation techniques in processors are inefficient due to the trade-off between page table size, leading to increased TLB misses and memory fragmentation, which affects overall processor performance.

Innovation Solution

Implementing a unified translation lookaside buffer (TLB) that supports multiple page sizes using a dynamic linked list, where the priority of page tables is adjusted based on program execution to optimize address translation performance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a unified TLB supports multiple page sizes with fixed priority, then device complexity is reduced, but address translation performance deteriorates due to increased TLB misses

Engineering Contradiction:
ImproveTLB structure complexityVSAvoidaddress translation performance
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent implements a dynamic priority mechanism where the TLB search order is adjusted based on runtime page size usage patterns. Instead of fixed priority, the system monitors which page sizes are accessed most frequently and reorders the TLB search sequence accordingly, allowing the structure to adapt its behavior dynamically while maintaining the unified design.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The system incorporates feedback loops that monitor TLB hit/miss rates for different page sizes and use this information to adjust the search priority order. The performance metrics are fed back to the control logic, which then modifies the TLB lookup sequence to optimize for the observed workload characteristics.

Inventive Principle:
Principle #23Feedback

2Reliability

If page table size is increased to reduce TLB misses, then memory fragmentation increases, but if page table size is decreased, then TLB misses increase

Engineering Contradiction:
ImproveTLB hit rateVSAvoidmemory fragmentation
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent changes the parameter being optimized from static page table size to dynamic search priority order. Instead of allocating more memory to page tables (which causes fragmentation), the system modifies the logical organization and access sequence of existing TLB entries based on runtime observations of page size usage patterns.

Inventive Principle:
Principle #35Parameter changes

Solution Approach 2:

The system applies different search priorities to different page size entries within the TLB based on their specific usage characteristics. Each page size category can have its own optimized position in the search sequence, allowing local optimization without affecting the global memory structure.

Inventive Principle:
Principle #3Local quality

3Measurement precision

If traditional separate TLBs are used for different page sizes, then address translation accuracy is improved, but device complexity increases

Engineering Contradiction:
Improveaddress translation accuracyVSAvoidTLB structure complexity
Core Design Contradiction:
Measurement precisionVSDevice complexity

Solution Approach 1:

The patent merges multiple separate TLB structures into a single unified TLB that handles all page sizes. The unified structure uses a prioritized search mechanism to maintain accuracy by systematically checking entries in order of likelihood, combining what would have been separate structures into one while preserving the precision of address translation.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The unified TLB is designed to be universal, handling multiple page sizes (4KB, 2MB, 1GB, etc.) within a single structure. The same TLB hardware and control logic can service different page size requirements by adjusting the search priority order, making the system multi-functional rather than requiring separate dedicated structures.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12499056B2Prioritized unified TLB lookup with variable page sizes
Publication Date: 2025.12.16 AKEANA INC
  • US12499056B2 patent drawing
  • US12499056B2 patent drawing
  • US12499056B2 patent drawing

AI summary

Techniques for address translation are disclosed. A processor core is accessed. The processor core includes a memory management unit (MMU) and a unified translation lookaside buffer (TLB) within the MMU. The TLB is configured to support a plurality of page sizes, and the processor core is coupled to an external memory system. The TLB receives a lookup request for a virtual memory address, wherein the virtual memory address corresponds to a process running on the processor core. The TLB accesses a linked list that comprises a page size priority order for the plurality of page sizes. A lookup is performed in the TLB on the virtual memory address, and the lookup is conducted in the page size priority order. The linked list is updated, the updating moves a page size associated with the lookup to a location in the linked list, and a physical address is returned.