Unified TLB with Size Flag for Multi-Page Address Translation
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Solution Overview
Problem
Modern high-performance processors require larger page sizes for address translation, but existing multi-TLB designs lead to low entry utilization and high power consumption due to the need for multiple TLBs to support various page sizes.
Innovation Solution
A memory management unit with a translation lookaside buffer that includes a size flag bit in each entry, allowing a single TLB to support multiple page sizes by dynamically selecting the appropriate page size for address translation, and a translation processing unit that looks up and translates virtual addresses based on the size flag bit.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a multi-TLB design is used to support multiple address translation sizes, then the adaptability for different page sizes is improved, but the device complexity and power consumption increase
Solution Approach 1:
The patent implements a single TLB that can support multiple address translation sizes (4KB, 16KB, 64KB, 256KB, 1MB, and 4MB pages) by adding a page size field to each TLB entry and modifying the translation logic. Instead of requiring separate TLBs for different page sizes, the unified TLB dynamically adapts to different page sizes through software configuration, thereby reducing hardware complexity while maintaining multi-size support capability.
2Adaptability or versatility
If a multi-TLB design is used to support multiple address translation sizes, then the adaptability for different page sizes is improved, but the power consumption increases
Solution Approach 1:
The patent merges multiple separate TLB structures into a single unified TLB that handles all address translation sizes. By consolidating what would otherwise require multiple independent TLB units into one structure, the patent reduces the total power consumption associated with maintaining and accessing multiple separate cache structures, while still providing support for various page sizes through logical differentiation rather than physical separation.
3Adaptability or versatility
If a multi-TLB design is used to support multiple address translation sizes, then the adaptability for different page sizes is improved, but the TLB entry utilization decreases
Solution Approach 1:
The patent introduces dynamic configurability to the TLB by adding a page size field to each entry and implementing runtime logic that adjusts translation behavior based on the configured page size. This dynamic approach allows the same physical TLB entries to be flexibly reused for different page sizes depending on the current system configuration, thereby maximizing entry utilization compared to static multi-TLB designs where each TLB is dedicated to a specific page size.
Data Source
AI summary
The present invention discloses a memory management unit, an address translation method, and a processor. The memory management unit includes: a translation lookaside buffer adapted to store a plurality of translation entries, where each translation entry includes a size flag bit, a virtual address tag, and a physical address tag, the virtual address tag represents a virtual page, the physical address tag represents a physical page corresponding to the virtual pane, and the size flag bit represents a page size of the virtual page; and a translation processing unit adapted to look up a translation entry whose virtual address tag matches a to-be-translated virtual address in the plurality of translation entries based on the page size represented by the size flag bit of the translation entry, and translate the virtual address into a physical address based on the matching translation entry.