Unified Tone Ordering Table for DSL Memory Efficiency

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Solution Overview

Problem

Existing DSL communication systems face inefficiencies in data throughput due to varying local loop conditions and require frequent updates to tone ordering and gain settings, which are not efficiently managed in current integrated circuits, leading to memory and computational challenges.

Innovation Solution

An integrated circuit with a memory and memory modification component that uses a single table to control bits count, gain, and tone order for discrete multi-tone sub-channels, allowing for in-service modifications to maintain reliable communication by coordinating changes between transceivers, thus conserving memory and improving data transmission efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If separate tables are used to store bits count, gain, and tone order for each sub-channel, then each parameter can be independently accessed and modified, but memory consumption increases and coordination between transceivers becomes complex

Engineering Contradiction:
ImproveIndependent parameter access and modificationVSAvoidMemory consumption
Core Design Contradiction:
Ease of operationVSQuantity of substance

Solution Approach 1:

The patent combines separate tables for bits count, gain, and tone order into a single unified table structure. Each entry in the table contains all three parameters for a given sub-channel, allowing independent access while reducing memory consumption by eliminating redundancy and reducing the number of separate data structures that need to be coordinated.

Inventive Principle:
Principle #5Merging (Combining)

2Reliability

If frequent updates to tone ordering and gain settings are performed to adapt to varying local loop conditions, then communication reliability is maintained, but computational complexity and memory operations increase

Engineering Contradiction:
ImproveCommunication reliability under varying conditionsVSAvoidComputational and memory operation complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent implements dynamic updating of the unified table to adapt to varying local loop conditions. The table can be modified in-service to change bits count, gain, and tone order for different sub-channels, allowing the system to respond to changing conditions without requiring complex computational routines or multiple data structures.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent uses a circular buffer approach where updates to the table are coordinated between transceivers. Instead of requiring complex synchronization of multiple separate tables, the system uses a simplified copying mechanism where changes are propagated through the unified table structure, reducing computational overhead while maintaining reliability.

Inventive Principle:
Principle #26Copying

3Ease of manufacture

If multiple separate tables are maintained for bits count, gain, and tone order, then parameter coordination between transceivers is straightforward, but memory consumption and data transmission overhead increase

Engineering Contradiction:
ImproveParameter coordination simplicityVSAvoidMemory and data transmission requirements
Core Design Contradiction:
Ease of manufactureVSQuantity of substance

Solution Approach 1:

The patent merges multiple separate parameter tables into a single unified table structure that contains all necessary parameters (bits count, gain, tone order) for each sub-channel. This reduces memory consumption and data transmission overhead while maintaining coordination simplicity through a consistent single-table interface that both transceivers use.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS7496134B2Computationally and memory efficient tone ordering scheme
Publication Date: 2009.02.24 TEXAS INSTRUMENTS INC
  • US7496134B2 patent drawing
  • US7496134B2 patent drawing
  • US7496134B2 patent drawing

AI summary

An integrated circuit 18 is provided that includes a memory 32 and a memory modification component 33. The memory 32 maintains a bits count, a gain, and a tone order for each of a plurality of discrete multi-tone sub-channels. The memory modification component 33 operable to control an in-service modification of at least some of the bits count, the gain, and the tone order using a single bits, gains and tone order table.