Unified VCAT/LCAS Unit for SDH and PDH Signals
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current solutions for implementing Virtual Concatenation (VCAT) and Link Capacity Adjustment Scheme (LCAS) are expensive and inefficient, as they require separate units for SDH and PDH links, leading to increased equipment costs and complexity, and do not efficiently handle Ethernet signals within the SONET/SDH frame structure.
Innovation Solution
A unified VCAT/LCAS unit is developed that can operate on both SDH and PDH links, utilizing a master and slave telecom bus architecture with GFP mapping, PDH units, and SDRAM for deskewing, which reduces memory needs and processes VLI frames efficiently, allowing for scalable and cost-effective bandwidth adjustment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If separate units are used for SDH and PDH links, then device functionality is comprehensive, but equipment cost and complexity increase
Solution Approach 1:
The patent combines separate SDH VCAT/LCAS units and PDH VCAT units into a single unified processor that can handle both signal types. The unified processor shares common resources including deskew buffers, VLI processors, and control logic, thereby reducing equipment cost and complexity while maintaining comprehensive functionality for both SDH and PDH links.
Solution Approach 2:
The unified VCAT/LCAS processor is designed with multi-functional capability to process both SDH and PDH signals through a single device. It includes configurable interfaces and processing paths that can adapt to different signal types, eliminating the need for separate dedicated units and achieving cost-effective versatility.
2Reliability
If separate units are used for SDH and PDH links, then signal processing capability is specialized, but equipment cost increases
Solution Approach 1:
The patent merges separate SDH and PDH processing units into a single unified processor that maintains specialized processing capabilities for each signal type through dedicated processing paths and configurable interfaces. This consolidation reduces equipment cost while preserving reliable signal processing through architecture that treats each signal type with appropriate specialized handling.
3Measurement precision
If traditional deskewing is implemented, then Ethernet signals are accurately aligned, but memory requirements increase
Solution Approach 1:
The patent implements partial deskewing by identifying and processing only the critical portion of out-of-order frames that require realignment. Instead of buffering and processing all frames completely, the system performs selective deskewing on frames that fall within the critical timing window, thereby achieving accurate alignment of Ethernet signals while significantly reducing memory requirements.
Solution Approach 2:
The patent extracts and processes only the essential deskewing operations needed for accurate Ethernet signal alignment, separating the critical alignment function from complete frame processing. By taking out only the necessary deskewing actions for out-of-order frames rather than processing all frames through full deskewing, memory requirements are reduced while maintaining alignment accuracy.
Data Source
AI summary
An apparatus for implementing VCAT in both SDH and PDH signals includes an SDH VCAT mapper coupled to a first telecom bus and a plurality of PDH units coupled to the first telecom bus and a second telecom bus. The PDH units read SDH VCAT bytes from the first telecom bus and write PDH VCAT bytes to the second telecom bus according to a gapped clock. At the data sink RS-Ack is determined before deskewing and is latched to be reported after deskewing. During deskewing, less than the maximum delay between members is tracked, thereby using less storage. Addressing of the deskewing storage is computed using a remainder algorithm.