Unified Vertex Cache and Shader Register File for GPU Data Movement

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Solution Overview

Problem

The existing GPU pipeline architecture faces bottlenecks due to the need to move large amounts of vertex attributes through multiple stages, which slows down image processing and increases power consumption, especially when handling primitives with many attributes.

Innovation Solution

Implementing a unified vertex cache and shader register file coupled with a shared shader that combines vertex and fragment shader cores, allowing vertex attributes to be stored and retrieved efficiently, thus eliminating the need for attribute data to be passed through the GPU pipeline, and deferring computationally intensive attribute gradient setup until necessary.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If vertex attributes are passed through each processing stage in the GPU pipeline, then data throughput is maintained, but processing speed decreases and power consumption increases

Engineering Contradiction:
Improveprocessing speedVSAvoidpower consumption
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent extracts vertex attributes from the main GPU pipeline data flow. Instead of passing all vertex attributes through each processing stage, the attributes are stored in a dedicated vertex cache memory structure that is accessible to shader cores when needed. This separation removes the bottleneck of moving large amounts of attribute data through the pipeline while maintaining access capability.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent introduces a vertex cache as an intermediary storage structure between the input data and the shader processing stages. The vertex cache holds vertex attributes and allows shader cores to retrieve them on-demand without requiring continuous data movement through the pipeline. This intermediary structure decouples the data storage from the processing flow, improving both speed and energy efficiency.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If a wide internal data bus is used to move large amounts of data through processing stages, then data throughput is improved, but device complexity and chip area increase

Engineering Contradiction:
Improvedata throughputVSAvoidchip area
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent extracts the vertex attribute storage function from the main data bus pathway. By implementing a separate vertex cache memory structure with its own address interface, the system eliminates the need for a wide data bus to carry all attribute data through the pipeline. The cache provides efficient access to attributes using narrower address buses, reducing overall device complexity and chip area.

Inventive Principle:
Principle #2Taking out (Extraction)

3Productivity

If dedicated register files are provided for each shader stage, then processing efficiency is improved, but device complexity and chip area increase

Engineering Contradiction:
Improveprocessing efficiencyVSAvoidchip area
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges the register files of different shader stages into a unified vertex cache structure. Instead of providing separate dedicated register files for vertex shaders, geometry shaders, and fragment shaders, the system uses a single shared cache that all shader cores can access. This consolidation maintains processing efficiency through fast access while significantly reducing the total chip area and device complexity compared to having multiple separate register files.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The vertex cache is designed as a universal storage structure that serves multiple shader stages and different types of vertex data. The same cache memory and address interface handle vertex attributes for various shader operations, making the system more versatile while reducing redundancy. This multi-functional approach eliminates the need for stage-specific register files while maintaining the required processing efficiency.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS7928990B2Graphics processing unit with unified vertex cache and shader register file
Publication Date: 2011.04.19 QUALCOMM INC
  • US7928990B2 patent drawing
  • US7928990B2 patent drawing
  • US7928990B2 patent drawing

AI summary

Techniques are described for processing computerized images with a graphics processing unit (GPU) using a unified vertex cache and shader register file. The techniques include creating a shared shader coupled to the GPU pipeline and a unified vertex cache and shader register file coupled to the shared shader to substantially eliminate data movement within the GPU pipeline. The GPU pipeline sends image geometry information based on an image geometry for an image to the shared shader. The shared shader performs vertex shading to generate vertex coordinates and attributes of vertices in the image. The shared shader then stores the vertex attributes in the unified vertex cache and shader register file, and sends only the vertex coordinates of the vertices back to the GPU pipeline. The GPU pipeline processes the image based on the vertex coordinates, and the shared shader processes the image based on the vertex attributes.