Unified Virtual Address Space Management via IOMMU TLB Sharing
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Solution Overview
Problem
In systems with multiple CPUs, each processor manages its own view of the virtual address space, leading to redundant software and hardware utilization, which wastes resources and lacks a mechanism for correcting page faults in peripheral devices.
Innovation Solution
A computing system with a host processor and a secondary processor, where the secondary processor presents an IOMMU-style interface, allowing the host processor to manage its TLB configuration and handle page faults, and can trade-off memory management duties based on operating mode, enabling the secondary processor to handle memory management for the host during low-power environments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If each processor manages its own virtual address space independently, then each processor can operate autonomously with its own MMU and page tables, but this leads to redundant software and hardware resources being utilized in each processor
Solution Approach 1:
The patent implements a unified virtual address space that can be shared across multiple processors, allowing the same page tables and translation resources to serve multiple CPUs simultaneously. The IOMMU is configured to use the host processor's page tables, enabling one set of memory management resources to universally serve both the host processor and secondary processors, thereby eliminating redundancy while maintaining operational capability.
Solution Approach 2:
The patent merges the memory management resources of multiple processors into a unified structure. The host processor's page tables are shared across the IOMMU and secondary processors, combining what would otherwise be separate MMU resources into a single shared resource pool. This consolidation eliminates duplicate page tables and reduces overall system complexity.
2Reliability
If the host processor manages memory management for the secondary processor, then page faults can be corrected through software handlers, but the host processor must remain active and powered on
Solution Approach 1:
The secondary processor is configured with its own MMU and TLB, enabling it to perform autonomous address translation and detect page faults independently. When a page fault occurs, the secondary processor can self-service by generating an interrupt to the host processor with the fault information, allowing the host to correct the issue and return control without needing to remain continuously active. This self-service capability reduces the host processor's power consumption while maintaining reliable page fault handling.
Solution Approach 2:
The system pre-configures the secondary processor with its own MMU and TLB resources, preparing it in advance to handle address translation and page fault detection autonomously. The secondary processor is pre-equipped with the capability to generate interrupts and communicate fault information to the host processor, so that when the host is powered down, the secondary can still manage its own memory operations and alert the host when needed, rather than requiring continuous host supervision.
3Speed
If the secondary processor has its own TLB, then address translation can be performed independently, but the TLB configuration and management becomes complex
Solution Approach 1:
The host processor acts as an intermediary for TLB management. The host processor's MMU manages the page tables, and the secondary processor's TLB is configured to use these same page tables. The host processor mediates TLB operations by handling page table updates and synchronizing translations across both processors. This intermediary approach allows the secondary processor to have its own TLB for fast address translation while avoiding the complexity of independent TLB management, as the host processor coordinates the translation resources.
Data Source
AI summary
Systems, apparatuses, and methods for managing a unified shared virtual address space. A host may execute system software and manage a plurality of nodes coupled to the host. The host may send work tasks to the nodes, and for each node, the host may externally manage the node's view of the system's virtual address space. Each node may have a central processing unit (CPU) style memory management unit (MMU) with an internal translation lookaside buffer (TLB). In one embodiment, the host may be coupled to a given node via an input/output memory management unit (IOMMU) interface, where the IOMMU frontend interface shares the TLB with the given node's MMU. In another embodiment, the host may control the given node's view of virtual address space via memory-mapped control registers.