Unified Virtual Memory Fault Buffer for Heterogeneous Processors

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Solution Overview

Problem

Traditional virtual memory systems for heterogeneous processors like CPUs and GPUs have independent memory management systems, leading to inefficiencies such as lack of cooperation for improved access latency and the need for application programmers to manage multiple types of pointers.

Innovation Solution

A unified virtual memory system using a page state directory that manages physical memory mappings, allowing memory pages to be migrated based on usage and providing a fault buffer for efficient execution of page faults.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If independent memory management systems are used for CPU and GPU, then each system can manage its own memory independently, but the systems cannot cooperate to improve access latency and programmers must manage multiple pointer types

Engineering Contradiction:
Improveindependent memory managementVSAvoidaccess latency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent merges the CPU memory management system and GPU memory management system into a unified virtual memory system. A single page table is shared between CPU and GPU, allowing both processors to access the same virtual address space. This unification enables cooperative memory management, where the systems can work together to optimize access latency through shared page fault handling and coordinated memory operations, while programmers need to manage only one type of pointer.

Inventive Principle:
Principle #5Merging (Combining)

2Adaptability or versatility

If independent memory management systems are used for CPU and GPU, then each system has its own page tables, but this increases system complexity and requires tracking multiple pointer types

Engineering Contradiction:
Improveindependent memory managementVSAvoidmemory management complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent combines multiple page tables into a single unified page table that serves both CPU and GPU. This single page table structure eliminates the need for separate page table management for each processor type, reducing the complexity of memory management. Programmers work with a single virtual address space and one type of pointer, while the unified system internally handles all address translation and memory management operations for both processors.

Inventive Principle:
Principle #5Merging (Combining)

3Adaptability or versatility

If separate page tables are maintained for CPU and GPU, then each processor has dedicated memory mappings, but this prevents memory page migration based on usage patterns

Engineering Contradiction:
Improvededicated memory mappingsVSAvoidmemory access efficiency
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The patent implements dynamic memory page migration capability within the unified virtual memory system. Memory pages can be automatically migrated between CPU memory and GPU memory based on usage patterns and access frequency. The unified page table maintains virtual-to-physical address mappings that can be dynamically updated as pages move between processors, enabling the system to optimize memory placement for performance without requiring separate static page tables for each processor.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS20230409486A1Fault buffer for tracking page faults in unified virtual memory system
Publication Date: 2023.12.21 NVIDIA CORP
  • US20230409486A1 patent drawing
  • US20230409486A1 patent drawing
  • US20230409486A1 patent drawing

AI summary

A system for managing virtual memory. The system includes a first processing unit configured to execute a first operation that references a first virtual memory address. The system also includes a first memory management unit (MMU) associated with the first processing unit and configured to generate a first page fault upon determining that a first page table that is stored in a first memory unit associated with the first processing unit does not include a mapping corresponding to the first virtual memory address. The system further includes a first copy engine associated with the first processing unit. The first copy engine is configured to read a first command queue to determine a first mapping that corresponds to the first virtual memory address and is included in a first page state directory. The first copy engine is also configured to update the first page table to include the first mapping.