Unified Virtual Memory for Heterogeneous System Architecture

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Solution Overview

Problem

Current GPU technology configures host and GPU memories as separate entities, leading to decreased processing speed and complex configuration due to the need for data transfer between them.

Innovation Solution

Implementing a heterogeneous system architecture with unified virtual memory that allows the host and HSA device to share memory, enabling parallel processing across multiple processor cores and offloading host operations onto the device.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If separate GPU memory (GDDR) is used instead of sharing main memory, then device memory capacity is improved, but data transfer complexity and time increase

Engineering Contradiction:
Improvedevice memory capacityVSAvoiddata transfer time
Core Design Contradiction:
Quantity of substanceVSLoss of time

Solution Approach 1:

The patent merges the host memory and device memory into a unified memory space, allowing both CPU and GPU to access the same physical memory without data transfer. This eliminates the need for separate GDDR memory while removing the associated data transfer overhead between host and device.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The unified memory architecture introduces a memory management unit that acts as an intermediary, handling address translation and memory allocation for both host and device simultaneously. This mediator enables direct memory sharing without requiring traditional data transfer protocols.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Adaptability or versatility

If separate GPU memory is used, then device independence is maintained, but system configuration complexity increases

Engineering Contradiction:
Improvedevice independenceVSAvoidinterface configuration complexity
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The unified memory architecture creates a universal memory interface that serves both host and device functions simultaneously. This single memory system performs multiple roles - serving as both host memory and device memory - thereby eliminating the need for separate interface configurations while maintaining device independence through virtual memory addressing.

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Stability of the object's composition

If data transfer between separate memories is required, then memory separation is maintained, but processing speed decreases

Engineering Contradiction:
Improvememory separationVSAvoidprocessing speed
Core Design Contradiction:
Stability of the object's compositionVSProductivity

Solution Approach 1:

The patent combines separate memory spaces into a unified memory architecture where host and device share the same physical memory resources. This merging eliminates data transfer operations entirely, as both CPU and GPU can directly access the same memory locations, thereby maintaining memory stability while dramatically improving processing speed.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11782835B2Host apparatus, heterogeneous system architecture device, and heterogeneous system based on unified virtual memory
Publication Date: 2023.10.10 ELECTRONICS & TELECOMM RES INST
  • US11782835B2 patent drawing
  • US11782835B2 patent drawing
  • US11782835B2 patent drawing

AI summary

Disclosed herein is a heterogeneous system based on unified virtual memory. The heterogeneous system based on unified virtual memory may include a host for compiling a kernel program, which is source code of a user application, in a binary form and delivering the compiled kernel program to a heterogenous system architecture device, the heterogenous system architecture device for processing operation of the kernel program delivered from the host in parallel using two or more different types of processing elements, and unified virtual memory shared between the host and the heterogenous system architecture device.