Uniform Electroless Plating via Equipotential Diffusion Barrier
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Solution Overview
Problem
In semiconductor device manufacturing, electro-less plating often results in uneven coating thicknesses on finely-patterned features due to potential differences, leading to reduced reliability of the semiconductor device.
Innovation Solution
A method involving the formation of a diffusion barrier layer between features on a substrate with different impurity regions, which connects the features electrically during electro-less plating and is then selectively removed to ensure uniform plating, using a seed layer and conductive materials like nickel, gold, and palladium, and subjecting the diffusion barrier layer to oxygen plasma treatment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If electro-less plating is used to deposit material on finely-patterned features, then the process requires less equipment and lower costs compared to electroplating, but variations in plating thickness occur due to potential differences between features
Solution Approach 1:
The patent applies equipotentiality by forming a conductive layer that electrically connects multiple features (bumps, wiring patterns) to a common potential. This is achieved by depositing a conductive material such as palladium, nickel, or copper over the features, and then selectively removing portions of this conductive layer to establish electrical connections between features while maintaining them at the same electrical potential during electro-less plating, thereby eliminating potential differences that cause non-uniform plating thickness
Solution Approach 2:
The patent uses an intermediary conductive layer (made of palladium, nickel, or copper) that acts as a mediator between the features and the plating solution. This intermediate conductive layer establishes a common electrical reference potential for all features, allowing the electro-less plating process to deposit uniform thicknesses on all features simultaneously without requiring complex equipment or high costs
2Adaptability or versatility
If features are electrically isolated by different impurity regions on the substrate, then each feature can be independently formed, but potential differences between features cause uneven plating during electro-less plating
Solution Approach 1:
The patent merges electrically isolated features into a common electrical potential by forming a continuous conductive layer that spans across multiple features. This conductive layer (comprised of palladium, nickel, or copper) is deposited over all features and then selectively removed to maintain electrical connections, effectively combining previously isolated features into a unified electrical system that enables uniform electro-less plating across all features
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures even electro-less plating thickness across features, enhancing the reliability of semiconductor devices by normalizing voltage potential and preventing uneven deposition.
Implementation Method 1
the diffusion barrier layer may provide an electrical path between the at least two features
Implementation Method 2
subjecting the diffusion barrier layer to oxygen plasma treatment
Implementation Method 3
electro-less plating an outer conductive layer on the at least two features
Data Source
AI summary
A method of manufacturing a semiconductor device includes forming a diffusion barrier layer on a substrate, and forming at least two features on the substrate such that the diffusion barrier layer is respectively disposed between each feature and the substrate and contacts the at least two features. A first impurity region of the substrate contains impurities of a first type, a second impurity region of the substrate contains impurities of a second type, different from the first type, a first feature of the at least two features is in the first impurity region, and a second feature of the at least two features is in the second impurity region, such that the second feature is electrically isolated from first feature by the different impurity regions.