Uniform Gap-Filling in High Aspect Ratio Semiconductor Gaps
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Solution Overview
Problem
Conventional semiconductor fabrication techniques face challenges in filling high aspect ratio gaps and openings, leading to void formation, nonuniform dielectric layers, and increased vulnerability to mobile ion contamination, resulting in leakage and low production yields, especially in miniaturized flash memory devices like mirrorbit devices.
Innovation Solution
A method involving the strategic deposition of multiple thin dielectric layers, each cured separately after deposition, to ensure uniform properties and prevent voids, using techniques like heating or UV radiation, with specific compositions for improved fluidity and contaminant gettering.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional single-layer deposition is used to fill high aspect ratio gaps, then the deposition process is simple and fast, but void formation occurs and the dielectric layer becomes nonuniform
Solution Approach 1:
The patent divides the single deposition process into multiple sequential deposition steps, where each step deposits a portion of the total dielectric layer thickness. Between deposition steps, the structure undergoes curing or annealing treatments. This segmentation allows each thin layer to be deposited uniformly without void formation, while maintaining overall process efficiency through automation.
2Device complexity
If conventional single-layer deposition is used to fill high aspect ratio gaps, then the process is simple, but voids form at the bottom of openings
Solution Approach 1:
The patent performs preliminary curing or annealing treatments on previously deposited layers before depositing subsequent layers. This preliminary action ensures that each layer is properly consolidated and adhered before adding more material, preventing void formation at the bottom of high aspect ratio gaps and ensuring complete, reliable gap filling.
3Reliability
If post deposition annealing is applied to improve dielectric layer density, then moisture resistance improves, but wet etch rate becomes nonuniform across the layer
Solution Approach 1:
The patent segments the annealing process into multiple separate annealing steps, each corresponding to a specific deposited layer. Each layer receives individualized heat treatment that optimizes its density and moisture resistance while maintaining uniform wet etch characteristics. This prevents the nonuniform etch rates that occur when a single annealing step is applied to the entire multi-layer structure.
4Productivity
If device dimensions are miniaturized to increase density, then device capacity increases, but vulnerability to mobile ion contamination increases
Solution Approach 1:
The patent enhances the dielectric material properties locally within the gap regions through targeted deposition and annealing processes. Each deposited layer is specifically treated to optimize its ability to trap and neutralize mobile ions, creating localized zones of high ion-gettering capability precisely where needed in the miniaturized device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in semiconductor devices with uniform gap-filling, reduced leakage, improved data retention, and increased reliability by ensuring homogeneous dielectric layers and uniform wet etch rates across the entire film thickness.
Implementation Method 1
curing the deposited first layer of dielectric material; depositing a second layer of dielectric material on the deposited first layer of dielectric material and into the gap; and curing the deposited second layer of dielectric material
Implementation Method 2
curing the deposited first layer of dielectric material; depositing a second layer of dielectric material on the deposited first layer of dielectric material and into the gap; and curing the deposited second layer of dielectric material
Data Source
AI summary
During semiconductor fabrication homogeneous gap-filling is achieved by depositing a thin dielectric layer into the gap, post deposition curing, and then repeating deposition and post deposition curing until gap-filling is completed. Embodiments include depositing a layer of low deposition temperature gap-fill dielectric into a high aspect ratio opening, such as a shallow trench or a gap between closely spaced apart gate electrode structures, as at a thickness of about 10 Å to about 500 Å, curing after deposition, as by UV radiation or by heating at a temperature of about 400° C. to about 1000° C., depositing another layer of low deposition temperature gap-filled dielectric, and curing after deposition. Embodiments include separately depositing and separately curing multiple layers.


