Uniform Grid Metal Gate With Trench Contact Cut for Dense Nanowire ICs

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

The scaling of multi-gate and nanowire transistors in integrated circuits poses challenges in maintaining mobility and short channel control, particularly due to constraints on lithographic processes, leading to trade-offs between feature dimension and spacing, and complex processing schemes are costly and introduce variation.

Innovation Solution

The implementation of a uniform grid metal gate and trench contact cut structure, using a 'plug-last' approach for gate dielectric and work function metal deposition, and employing angled plasma etching for self-aligned plug removal, simplifies the process and reduces cost and variation.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If conventional multi-gate transistor fabrication processes are used, then device density increases through scaling, but process complexity and cost increase significantly

Engineering Contradiction:
Improvedevice densityVSAvoidprocess complexity
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The fabrication process is divided into distinct stages: forming gate dielectric plugs in isolation trenches, depositing work function metal, and selectively removing plugs. This segmentation allows each step to be optimized independently, reducing overall process complexity while maintaining high device density

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Gate dielectric plugs are formed in isolation trenches before metal gate deposition. This preliminary action establishes the final gate structure geometry early in the process, enabling subsequent metal deposition to proceed without additional patterning steps, thereby reducing complexity

Inventive Principle:
Principle #10Preliminary action

2Productivity

If feature dimensions are reduced to increase device density, then capacity increases, but lithographic process constraints worsen

Engineering Contradiction:
Improvedevice densityVSAvoidlithographic process precision
Core Design Contradiction:
ProductivityVSManufacturing precision

Solution Approach 1:

The isolation trenches extend vertically through the substrate, utilizing the depth dimension to achieve electrical isolation. This allows lateral feature sizes to be reduced for higher density without compromising isolation effectiveness, as the vertical trench depth provides the isolation mechanism

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

3Productivity

If tight endcap spacing is maintained for high density, then device capacity increases, but process variation and defects increase

Engineering Contradiction:
Improvedevice capacityVSAvoidprocess robustness
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The work function metal deposition process is self-aligned to the gate dielectric plug edges, automatically establishing the correct endcap spacing. This self-service mechanism eliminates the need for additional lithographic alignment steps, reducing process variation and defects while maintaining tight spacing for high capacity

Inventive Principle:
Principle #25Self-service

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach enhances device performance by reducing process complexity, improving robustness, and allowing for seamless work function metal deposition, while maintaining tight endcap spacing and reducing defects.

Implementation Method 1

employing angled plasma etching for self-aligned plug removal

Methodology Applied
Scientific EffectPlasma etching: Plasma

Data Source

PatentUS20240105716A1Integrated circuit structures having uniform grid metal gate and trench contact plug
Publication Date: 2024.03.28 INTEL CORP
  • US20240105716A1 patent drawing
  • US20240105716A1 patent drawing
  • US20240105716A1 patent drawing

AI summary

Integrated circuit structures having uniform grid metal gate and trench contact cut, and methods of fabricating integrated circuit structures having uniform grid metal gate and trench contact cut, are described. For example, an integrated circuit structure includes a vertical stack of horizontal nanowires. A gate electrode is over the vertical stack of horizontal nanowires. A conductive trench contact is adjacent to the gate electrode. A dielectric sidewall spacer is between the gate electrode and the conductive trench contact. A first dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact. A second dielectric cut plug structure extends through the gate electrode, through the dielectric sidewall spacer, and through the conductive trench contact, the second dielectric cut plug structure laterally spaced apart from and parallel with the first dielectric cut plug structure.