Uniform Grid Metal Gate With Pixelized VT Adjustment
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Solution Overview
Problem
The challenge of maintaining mobility improvement and short channel control in microelectronic devices as device dimensions scale below the 10 nanometer node, particularly in multi-gate and nanowire transistors, is exacerbated by constraints on lithographic processes and the trade-off between feature pattern dimensions and spacing.
Innovation Solution
The implementation of a uniform grid metal gate and trench contact cut structure, combined with a pixelized gate voltage threshold (VT) adjustment, which involves a metal gate process with trench contact plugs and localized plug removal to adjust VT variability, and the use of dipoles to set threshold voltage, enabling seamless work function metal deposition and reducing process variation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device dimensions are scaled down to increase density, then capacity increases, but mobility improvement and short channel control deteriorate
Solution Approach 1:
The patent transitions from planar 2D channel structures to three-dimensional nanowire structures with gate-all-around configuration. This dimensional change enables the gate to control the channel from all directions (top, bottom, and sidewalls), providing superior electrostatic control and short channel effect suppression at scaled dimensions while maintaining high device density through vertical stacking of multiple nanowires.
Solution Approach 2:
The patent employs composite material structures including high-k dielectric materials combined with metal gate electrodes, and semiconductor nanowires with silicon germanium sacrificial layers. These composite materials enable improved carrier mobility, better gate control, and enhanced thermal stability, addressing the reliability challenges associated with scaled dimensions.
2Quantity of substance
If device dimensions are scaled down to increase density, then capacity increases, but mobility improvement deteriorates
Solution Approach 1:
The patent employs composite material structures including high-k dielectric materials combined with metal gate electrodes, and semiconductor nanowires with silicon germanium sacrificial layers. These composite materials enable improved carrier mobility, better gate control, and enhanced thermal stability, addressing the reliability challenges associated with scaled dimensions.
Solution Approach 2:
The transition to three-dimensional nanowire structures with gate-all-around configuration reduces scattering effects at interfaces and improves carrier transport pathways, thereby maintaining mobility even as dimensions scale down.
3Manufacturing precision
If lithographic processes are used to pattern features, then device fabrication is enabled, but spacing constraints between features worsen
Solution Approach 1:
By moving to three-dimensional nanowire structures with gate-all-around configuration, the patent reduces the lateral footprint of each device. Multiple nanowires can be vertically stacked within a smaller planar area, thereby increasing device density while maintaining adequate spacing between adjacent devices and simplifying lithographic patterning requirements.
Solution Approach 2:
The patent segments the channel into multiple discrete nanowires stacked vertically, with each nanowire independently controlled by the gate. This segmentation allows for more flexible layout arrangements and reduces the spacing constraints between features, as the vertical stacking enables tighter lateral packing.
4Ease of manufacture
If uniform grid metal gate and trench contact cut structure is implemented, then manufacturing complexity is reduced, but VT adjustment precision is limited
Solution Approach 1:
The patent introduces pixelized gate voltage threshold adjustment that enables localized modification of the gate structure at specific device locations while maintaining the overall uniform grid architecture. This local quality approach allows for precise VT control at individual device or small group levels without compromising the manufacturing simplicity of the global uniform structure.
Solution Approach 2:
The gate structure is segmented into pixelized regions that can be independently adjusted. This segmentation enables precise VT control at localized areas while maintaining the simplicity of uniform grid fabrication for the majority of the device array, effectively resolving the contradiction between manufacturing ease and adjustment precision.
Data Source
AI summary
Integrated circuit structures having uniform grid metal gate and trench contact cut are described. For example, an integrated circuit structure includes a first and second vertical stacks of horizontal nanowires or fins. A first gate structure is over the first vertical stack of horizontal nanowires or fin, and a second gate structure is over the second vertical stack of horizontal nanowires or fin, the second gate structure having voltage threshold (VT) different than a VT of the first gate structure. A conductive trench contact is adjacent to the first gate structure and the second gate structure. A dielectric sidewall spacer is between the first gate structure and the conductive trench contact, and between the second gate structure and the conductive trench contact. A dielectric cut plug structure is extending between the first gate structure and the second gate structure, through the dielectric sidewall spacer, and through the conductive trench contact.