Uniform Low-k Inner Spacer Module for GAA Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for forming inner spacers in stacked nanosheet structures face challenges in achieving uniformity and preventing parasitic capacitance, which leads to issues like gate length variability and defects due to low selectivity between silicon nitride and silicoboron carbonitride, and inner spacer lift-off during replacement metal gate fabrication.
Innovation Solution
A method involving the formation of a nanosheet stack with alternating sacrificial layers, followed by the deposition of oxide materials and their nitridization to create uniform low-k inner spacers using ammonia diffusion-limited rapid thermal nitridation, ensuring improved spacer boundaries and compatibility with RMG processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon nitride inner spacers are formed in stacked nanosheet structures, then the inner spacers provide structural support and electrical isolation, but low selectivity between silicon nitride and silicoboron carbonitride causes gate length variability and defects
Solution Approach 1:
The patent applies local quality by creating distinct regions with different nitrogen concentrations within the inner spacer structure. The method forms a first inner spacer layer with lower nitrogen concentration (from silicon dioxide) and a second inner spacer layer with higher nitrogen concentration (from silicoboron carbonitride), where each layer serves specific local functions. This gradient structure provides both structural support and electrical isolation while enabling selective etching to achieve uniform gate lengths.
Solution Approach 2:
The patent uses composite materials by combining silicon dioxide and silicoboron carbonitride in a layered inner spacer structure. The first inner spacer layer uses silicon dioxide as the base material, and the second inner spacer layer uses silicoboron carbonitride, creating a composite structure that leverages the advantages of both materials - the electrical isolation properties of silicon dioxide and the structural stability of silicoboron carbonitride.
2Reliability
If replacement metal gate fabrication is performed, then advanced device performance is achieved, but inner spacer lift-off occurs during the process
Solution Approach 1:
The patent applies preliminary action by forming the dual-layer inner spacer structure before the replacement metal gate fabrication process. The first inner spacer layer (silicon dioxide) is formed as a base structure, and the second inner spacer layer (silicoboron carbonitride) is subsequently formed on top. This pre-formed layered structure is designed to withstand the subsequent RMG fabrication processes, preventing lift-off by providing a stable, multi-layer foundation that maintains integrity during metal gate formation.
3Ease of manufacture
If conventional inner spacer formation methods are used, then fabrication is simpler, but parasitic capacitance increases and uniformity is poor
Solution Approach 1:
The patent applies parameter changes by modifying the nitrogen concentration and material composition parameters of the inner spacer. Instead of using a single uniform material, the method varies the nitrogen content across different layers - the first layer has lower nitrogen concentration (silicon dioxide) and the second layer has higher nitrogen concentration (silicoboron carbonitride). This parameter variation reduces parasitic capacitance while maintaining fabrication feasibility through sequential deposition processes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the creation of sharp, well-defined inner spacers that reduce parasitic capacitance and gate length variability, enhancing process control and preventing defects, thereby improving the scalability and performance of nanosheet FETs.
Implementation Method 1
deposition of oxide materials and their nitridization to create uniform low-k inner spacers using ammonia diffusion-limited rapid thermal nitridation
Implementation Method 2
portions of the oxide material are nitridized to form inner spacers positioned between the adjacent ones of the multiple nanosheets
Data Source
AI summary
Embodiments are directed to a method of forming a stacked nanosheet and resulting structures having uniform low-k inner spacers. A nanosheet stack is formed opposite a major surface of a substrate. The nanosheet stack includes multiple nanosheets. Cavities are formed between adjacent ones of the multiple nanosheets. The cavities are filled with an oxide material and portions of the oxide material are nitridized to form inner spacers positioned between the adjacent ones of the multiple nanosheets.