Uniform Poly Silicon Transistor Gate for Current Source Arrays
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Solution Overview
Problem
In integrated circuit design, the non-uniform poly silicon density in transistors leads to performance issues, including increased parasitic capacitance and reduced operation speed due to complex wire routing and gradients in poly silicon density, affecting the overall performance of current source units.
Innovation Solution
The use of transistors with uniform poly silicon density, achieved by constructing the gate terminal from multiple separated poly silicon slices, and arranging current source units in a symmetrical array with dummy cells to reduce the influence of poly silicon density gradients, thereby increasing output impedance and simplifying wire routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the gate terminal is constructed with traditional continuous poly silicon, then the manufacturing process is simple, but the poly silicon density is non-uniform causing performance issues
Solution Approach 1:
The gate terminal is divided into multiple separated poly silicon segments instead of using a continuous poly silicon structure. This segmentation creates uniform poly silicon density distribution, reducing gradient effects and improving transistor performance while maintaining manufacturing feasibility through standard photolithography processes
2Speed
If complex wire routing is used to achieve connections, then the circuit functionality is complete, but parasitic capacitance increases and operation speed decreases
Solution Approach 1:
Adjacent current source units share common wire routing paths and poly silicon structures, merging redundant connections into shared resources. This reduces the total wire length and number of routing layers required, thereby decreasing parasitic capacitance and improving operation speed while maintaining complete circuit functionality
3Manufacturing precision
If current source units are arranged without symmetry, then the layout flexibility is high, but poly silicon density gradients affect performance
Solution Approach 1:
The patent employs symmetrical arrangement of current source units in the array, where units are positioned in mirror-image patterns around a central axis. This symmetrical layout ensures uniform poly silicon density distribution across the array, eliminating density gradients that would otherwise degrade performance, while still providing adequate layout flexibility for circuit integration
Data Source
AI summary
A transistor with uniform density of poly silicon includes a gate terminal, a drain terminal, and a source terminal. The gate terminal is constructed by a plurality of separated poly silicon, such that the density of the poly silicon is uniform.