Uniform Sidewall Epitaxy for Embedded Source/Drain
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional methods for forming embedded epitaxial material in source/drain regions of transistors face challenges such as increased contact resistance and performance degradation due to variations in dopant concentrations and thickness, particularly in FinFET structures where epitaxial regions are formed thinly near the gate structure.
Innovation Solution
A method involving the formation of a first epitaxial region with substantially uniform sidewall thickness in the source/drain regions, followed by the removal of a portion using a spacer layer as a mask, and subsequent growth of a second epitaxial region to create an embedded source/drain structure, which reduces resistance and improves drive current at the contact interface.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If epitaxial material is grown to create larger landing area for contact structures, then contact area is increased, but uniformity of epitaxial thickness becomes difficult to achieve
Solution Approach 1:
The patent employs spacer structures formed prior to the epitaxial growth process to define precise boundaries and thickness control for the embedded epitaxial material. The spacers are formed on the sidewalls of the gate structure before epitaxial growth, creating a template that ensures uniform thickness of the first epitaxial region adjacent to the gate. This preliminary structuring enables controlled growth with uniform dimensions while still achieving the desired larger contact area through the extended second epitaxial region.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in reduced contact resistance and enhanced performance by ensuring uniform epitaxial thickness, thereby improving the interface between the source/drain regions and contact structures, leading to better transistor performance.
Implementation Method 1
Source/drain region formation may include the growth of epitaxial material to create a larger landing area for contact structures
Implementation Method 2
removing a first portion of the first epitaxial region using the first spacer layer as a mask
Data Source
AI summary
A semiconductor structure including a source/drain region is disclosed. The source/drain region may include a first epitaxial region along at least one sidewall of the source/drain region having a substantially uniform sidewall thickness. The semiconductor structure may further include a gate structure adjacent and above the source/drain region wherein at least a portion of the first epitaxial region is positioned below a sidewall spacer of the gate structure. A method of forming a source/drain region including a first epitaxial region having a substantially uniform sidewall thickness is disclosed. The method may include forming a trench in a substrate adjacent to a gate structure, forming the first epitaxial region in the trench, forming a spacer material layer on the gate structure and on a portion of the first epitaxial region, and removing a portion of the first epitaxial region using the spacer material layer as a mask.