Unit Cell Arrays with Micro Pads for 3D IC Fault Detection

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Solution Overview

Problem

As three-dimensional integrated circuit (3D IC) structures become more complex, it becomes increasingly challenging and time-consuming to identify faulty components such as conductive lines and vias due to the complexity of signal paths and the need for extended timing budgets in fault detection systems.

Innovation Solution

The implementation of arrays of unit cells with micro pad structures, where each unit cell includes programmable design parameters and micro pad structures for electrical connections, allows for efficient identification of faulty components by dividing the circuit layout into smaller regions, enabling simultaneous and parallel testing through macro pad structures and precise signal paths.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If 3D IC structures are made more complex with additional layers and components, then functionality and integration density are improved, but fault detection difficulty and time consumption increase

Engineering Contradiction:

Improveintegration densityVSAvoidfault detection difficulty

Core Design Contradiction:

Adaptability or versatilityVSDifficulty of detecting and measuring

Solution Approach 1:

The circuit layout is divided into multiple regions, with each region containing a subset of unit cells. Test structures are distributed across these regions, allowing fault detection to be performed in a segmented manner rather than as a single complex test, thereby reducing detection difficulty in highly integrated 3D IC structures

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Test structures including pad structures and conductive paths are introduced as intermediary elements between the complex integrated components and the fault detection system. These intermediaries provide accessible test points and simplified signal paths that mediate between the high-density internal structure and external testing equipment

Inventive Principle:

Principle #24Intermediary (Mediator)

2Productivity

If circuit layout is divided into smaller regions with unit cells, then fault identification efficiency is improved, but device complexity increases

Engineering Contradiction:

Improvefault identification efficiencyVSAvoidcircuit structure complexity

Core Design Contradiction:

ProductivityVSDevice complexity

Solution Approach 1:

Unit cells are designed as universal, standardized building blocks that can be repeatedly instantiated across different regions of the circuit layout. Each unit cell contains the same essential functionality and test structure configuration, allowing the system to achieve high fault identification efficiency through modular repetition rather than through genuinely complex heterogeneous structures

Inventive Principle:

Principle #6Universality (Multi-functionality)

Solution Approach 2:

The circuit layout parameters such as region dimensions, unit cell density, and test structure spacing are optimized to balance fault identification efficiency with overall device complexity. By adjusting these parameters, the system achieves efficient fault localization without excessive structural complexity

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS20240369626A1Array of unit cells having pad structures

Publication Date: 2024.11.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

The present disclosure describes a method that includes scanning a circuit layout and identifying layout regions of the circuit layout. The method further includes placing unit cells in a layout region of the layout regions and forming a micro pad structure at a border of a unit cell of the unit cells. The micro pad structure includes interconnect structures that are electrically connected to the unit cell.