Unit Delay Circuit Path Switching for Glitch-Free Delay Updates
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Solution Overview
Problem
Conventional digitally controlled delay lines generate glitches when the delay code changes, leading to malfunctions in circuits that operate synchronously with clock signals due to differences in the number of edges between input and output signals.
Innovation Solution
A unit delay circuit with multiple paths and control circuits that adjust the delay based on a selection code, preventing glitches by ensuring the number of edges in the input and output signals remains consistent, using a first path when the selection signal is inactivated and a third path when activated, and updating the selection code at specific trigger signal edges.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the delay code is changed in a conventional digitally controlled delay line, then the delay amount is adjusted, but a glitch is generated in the output signal
Solution Approach 1:
The patent applies preliminary action by preparing multiple delay paths in advance (first delay path with first delay amount, second delay path with second delay amount) and pre-calculating the selection timing. When a delay code change is detected, the system has already prepared the appropriate delay path and selection timing information, allowing seamless switching without glitches. This resolves the contradiction by enabling delay amount adjustment while maintaining signal stability through pre-prepared transition paths.
Solution Approach 2:
The patent implements dynamics by dynamically selecting between multiple delay paths based on the delay code and timing. The system transitions from static delay configuration to dynamic path selection, where the first path selection signal and second path selection signal are generated based on the current delay code and timing information. This dynamic switching mechanism allows the delay amount to be adjusted while preventing glitches, resolving the contradiction between adaptability and signal stability.
2Reliability
If multiple delay paths are added to prevent glitches, then signal stability improves, but circuit complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the delay function into multiple independent delay paths (first delay path, second delay path), each handling specific delay amounts. This segmentation allows the system to switch between predefined delay configurations without complex real-time adjustments. By segmenting the delay function into manageable paths with associated selection signals, the patent achieves signal stability while controlling circuit complexity through modular design.
Solution Approach 2:
The patent uses partial action by implementing only the necessary delay paths and selection mechanisms required for glitch-free operation. Rather than creating all possible delay paths, the system implements specific first and second delay paths with corresponding selection signals, updating paths only when delay code changes occur. This selective implementation maintains signal stability while avoiding unnecessary circuit complexity from excessive path creation.
Data Source
AI summary
In an embodiment, a unit delay circuit comprises a first path configured to delay a first input signal to output a first output signal when a selection signal is inactivated, a second path configured delay a second input signal to output a second output signal when the selection signal is inactivated, and a third path configured to delay the first input signal to output the second output signal when the selection signal is activated.