Unit-Distance Coding for Replacement Gate QLC Memory
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Solution Overview
Problem
Memory devices with replacement gate configurations are susceptible to significant voltage shifts due to charge loss, leading to higher bit error rates, especially at higher voltage threshold levels in multi-level cell configurations like quad-level cells (QLCs).
Innovation Solution
Implementing improved unit-distance/Gray code schemes that distribute page types more evenly across voltage threshold distributions, avoiding clustering of page types at higher voltage threshold levels and accounting for asymmetric voltage shifts, thereby reducing the overall raw bit error rate (RBER).
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If replacement gate configuration is used in multi-level cell memory, then manufacturing complexity is reduced and ease of manufacture is improved, but voltage shifts due to charge loss increase leading to higher bit error rates
Solution Approach 1:
The patent changes the voltage threshold parameters by implementing asymmetric voltage shifts tailored to different page types. Instead of uniform voltage thresholds, the system applies differentiated voltage shift compensation specifically targeting pages prone to higher error rates due to replacement gate characteristics, thereby improving reliability while maintaining manufacturing simplicity
Solution Approach 2:
The patent applies local quality by treating different page types (e.g., lower page, upper page, extra page, top page) differently in the coding scheme. Each page type receives customized voltage shift compensation based on its specific error susceptibility, rather than applying a uniform approach across all pages. This localized treatment addresses the specific reliability issues of replacement gate memory without compromising overall manufacturing ease
2Device complexity
If conventional coding schemes are used in replacement gate memory, then device complexity is low, but voltage threshold clustering at higher levels increases bit error rates
Solution Approach 1:
The patent introduces asymmetry into the coding scheme by implementing asymmetric voltage shifts for different page types. Rather than symmetric treatment of all pages, the system deliberately applies different voltage compensation strategies to lower, upper, extra, and top pages based on their specific error characteristics. This asymmetric approach directly addresses the voltage threshold clustering problem in replacement gate memory while adding minimal complexity
Solution Approach 2:
The patent segments the coding scheme into distinct components for different page types. Instead of a single uniform coding approach, the system divides the error correction strategy into separate handling for lower pages, upper pages, extra pages, and top pages. This segmentation allows targeted optimization for each page type's specific voltage shift characteristics, reducing overall bit error rates without significantly increasing device complexity
Data Source
AI summary
Methods, systems, and devices for coding for quad-level memory cells having a replacement gate configuration are described. Data may be received for storage in a memory device that includes a memory array with memory cells having a replacement gate configuration. The data may be assigned to a plurality of different types of pages within a memory cell of the memory cells using a unit-distance code. The data may be written to the plurality of pages of the different types within the memory cell based at least in part on assigning the data to the plurality of pages of the different types within the memory cell using the unit-distance code to distribute the pages in a way to avoid inconsistent voltage shifting across the plurality of pages of different types.