Unit MOS Device Arrays for Integrated Circuit Layout
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Solution Overview
Problem
The increasing demand for higher drive currents and higher device densities in semiconductor devices, particularly with the introduction of FinFETs, complicates the design of integrated circuits due to alignment challenges and reduced overlay windows, leading to potential device failures and complexity in manufacturing.
Innovation Solution
A semiconductor structure and method involving arrays of unit metal-oxide-semiconductor (MOS) devices with active regions and gate electrodes laid out in specific directions, allowing for the formation of interconnected MOS devices with varying conductivity types and contact configurations to enhance drive currents and simplify design, while reducing misalignment issues and complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If MOS device gate width is increased to increase drive current, then drive current increases, but device area increases reducing device density
Solution Approach 1:
The patent segments MOS devices into unit devices arranged in arrays, where each unit device has a standardized gate width. Multiple unit devices can be connected in parallel to achieve higher drive currents without increasing the area of individual devices, thus maintaining high device density while providing flexible drive current scaling.
Solution Approach 2:
The patent merges multiple unit MOS devices into arrays with shared contacts and interconnect structures. By combining multiple unit devices that share common source/drain contacts and gate electrodes, the effective drive current increases while the area overhead is minimized, resolving the contradiction between drive current and device density.
2Productivity
If device density is increased to integrate more functions, then device density increases, but overlay window decreases making alignment more difficult
Solution Approach 1:
The patent segments the circuit into repeating unit device arrays with standardized geometries. This segmentation creates self-aligned structures where features are defined by the same mask patterns repeated across the array, effectively increasing the overlay window despite high device density by reducing sensitivity to misalignment.
Solution Approach 2:
The patent changes the geometric parameters of unit devices to create self-aligned configurations. By designing unit devices with specific dimensional relationships and symmetries, the structures automatically align during fabrication, enlarging the effective overlay window and enabling high device density without compromising manufacturing precision.
3Power
If FinFET is used to increase drive current, then drive current increases, but alignment precision requirement increases due to small fin size
Solution Approach 1:
The patent segments FinFET structures into unit devices within arrays, where each FinFET has a standardized fin size and geometry. The array configuration with shared contacts and interconnects reduces the overall alignment precision requirement by distributing the alignment tolerance across multiple repeating units, making the fabrication process more robust despite the small fin dimensions.
4Adaptability or versatility
If customized active regions and gate electrodes are formed for each MOS device, then device performance is optimized, but design complexity and manufacturing complexity increase
Solution Approach 1:
The patent segments MOS devices into standardized unit devices with identical active regions and gate electrode configurations. This segmentation allows for simplified manufacturing with reduced design complexity, while still enabling performance optimization through the selection and arrangement of unit devices in arrays, and through post-fabrication customization of interconnect configurations.
Solution Approach 2:
The patent creates universal unit device structures that can serve multiple functions and configurations. The standardized unit devices with common active regions and gate electrodes can be arranged in different patterns and connected through various interconnect schemes to achieve different device performances, reducing both design and manufacturing complexity while maintaining versatility.
Data Source
AI summary
A semiconductor structure includes an array of unit metal-oxide-semiconductor (MOS) devices arranged in a plurality of rows and a plurality of columns is provided. Each of the unit MOS devices includes an active region laid out in a row direction and a gate electrode laid out in a column direction. The semiconductor structure further includes a first unit MOS device in the array and a second unit MOS device in the array, wherein active regions of the first and the second unit MOS devices have different conductivity types.