Unit Specific Alignment and Routing for Semiconductor Die Shift Compensation
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Solution Overview
Problem
Conventional semiconductor packaging methods face challenges in efficiently addressing die shift and misalignment during processing, leading to yield loss, increased capture pad size, and reduced interconnect density due to the need for large design rule values and high-accuracy die attach tools.
Innovation Solution
The method involves forming an embedded die panel with conductive interconnects and measuring the actual position of semiconductor dies to create a build-up interconnect structure with unit specific alignment and routing, allowing for adaptive alignment and routing to compensate for die shifts and rotations, thereby minimizing yield loss and increasing interconnect density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If large capture pad sizes are used to account for die shift, then manufacturing yield is maintained, but interconnect density is reduced
Solution Approach 1:
The patent divides the interconnect structure into multiple segments: fixed capture pads, movable alignment portions, and routing portions. Each segment can be independently positioned and adjusted, allowing the capture pads to be smaller while maintaining alignment through the movable portions that compensate for die shift.
Solution Approach 2:
The patent introduces dynamic alignment portions that can be repositioned based on measured die positions. The alignment portions are not fixed but can be adjusted to match the actual position of each die, enabling smaller capture pads while maintaining manufacturing yield through adaptive realignment.
2Manufacturing precision
If high-accuracy die attach tools are used to minimize die shift, then manufacturing precision is improved, but device complexity and cost increase
Solution Approach 1:
The patent enables the interconnect structure to self-correct for die shift through measured alignment portions. Instead of relying on high-precision equipment to prevent shift, the system measures the actual shift and automatically compensates through reconfigurable alignment portions, making the process self-correcting and less dependent on expensive equipment.
Solution Approach 2:
The patent implements a feedback mechanism where die positions are measured after attachment, and this measurement information is used to adjust the alignment portions accordingly. This closed-loop approach allows standard equipment to achieve high precision outcomes through measurement and compensation rather than relying solely on equipment precision.
3Manufacturing precision
If large design rule values are used to accommodate die misalignment, then manufacturing precision tolerance is increased, but interconnect density is reduced
Solution Approach 1:
The patent segments the interconnect design into fixed capture pads, movable alignment portions, and routing portions. This segmentation allows the capture pads to be smaller with tighter design rules, while the movable alignment portions provide the necessary tolerance for misalignment without requiring large overall design rule values.
Solution Approach 2:
The patent changes the positional parameters of alignment portions based on measured die positions. By dynamically adjusting the position parameters of alignment portions rather than using fixed large design rules, the system achieves high alignment tolerance while maintaining small feature sizes and high interconnect density.
4Device complexity
If conventional fixed alignment methods are used, then device complexity is minimized, but adaptability to die shift is reduced
Solution Approach 1:
The patent transforms the static alignment structure into a dynamic one where alignment portions can be repositioned based on measured die positions. This dynamic capability allows the system to adapt to various die shift scenarios while maintaining a relatively simple base structure that can be configured for different alignment requirements.
Solution Approach 2:
The patent creates a universal alignment system where the same interconnect structure with reconfigurable alignment portions can accommodate different die positions and orientations. The alignment portions serve multiple functions: initial alignment, shift compensation, and routing connection, reducing the need for separate specialized structures.
Data Source
AI summary
A method of making a semiconductor device can include forming an embedded die panel by encapsulating a first semiconductor die and a second semiconductor die with conductive interconnects in a single step. An actual position of the first semiconductor die and second semiconductor die can be measured within the embedded die panel. The first semiconductor die and the second semiconductor die can be interconnected by a build-up interconnect structure comprising a first unit specific alignment portion aligned with the first semiconductor die, a second unit specific alignment portion aligned with the second semiconductor die, unit specific routing connecting the first unit specific alignment portion and the second unit specific alignment portion, and a fixed portion aligned with outline of embedded die panel and coupled to the unit specific routing.