Unitary Source/Drain Contacts for Dense IC Packing
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Solution Overview
Problem
The challenge in manufacturing densely packed integrated circuit products is the complexity and cost associated with forming precise conductive structures, particularly in reducing the vertical height of contact elements and metallization layers, which affects the packing density and performance due to the need for multiple masking layers and complex lithography techniques.
Innovation Solution
The approach involves forming a single unitary conductive source/drain contact structure that spans across isolation regions, reducing the number of masking layers required and enabling a more efficient formation of conductive structures, thereby decreasing the overall vertical height and capacitance of the device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple separate conductive structures are formed for each source/drain region, then precise electrical contact is achieved, but the vertical height and device complexity increase due to multiple masking layers and lithography techniques
Solution Approach 1:
The patent merges multiple separate conductive structures into a single unitary conductive structure that contacts multiple source/drain regions simultaneously. This is achieved by forming one continuous conductive material layer that spans across isolation regions, eliminating the need for multiple separate contact structures and their associated masking layers, thereby reducing device complexity while maintaining manufacturing precision
Solution Approach 2:
The unitary conductive structure serves multiple functions: it provides electrical contact to multiple source/drain regions, acts as a common interconnect, and reduces the overall vertical height of the device. This multi-functional approach eliminates the need for separate contact structures for each source/drain region, reducing both complexity and vertical dimension
2Manufacturing precision
If multiple masking layers and complex lithography techniques are used to form precise conductive structures, then contact precision is improved, but manufacturing cost and process complexity increase
Solution Approach 1:
The patent combines multiple lithography and masking operations into a single process step by forming one continuous conductive structure that contacts multiple source/drain regions. This eliminates the need for multiple masking layers and complex lithography techniques, significantly simplifying the manufacturing process while maintaining the precision required for proper electrical contact
Solution Approach 2:
The patent uses a single masking layer with multiple patterned regions to define contact openings for multiple source/drain regions simultaneously. This segmented approach within a single masking layer allows precise alignment and contact formation without requiring multiple sequential masking and lithography steps, reducing process complexity
3Area of moving object
If the vertical height of contact elements and metallization layers is reduced to increase packing density, then area occupancy decreases, but the formation of precise conductive structures becomes more difficult
Solution Approach 1:
The patent transitions from vertical stacking of multiple separate contact structures to a lateral extension of a single unitary conductive structure. By forming one continuous conductive layer that spans across isolation regions in the lateral dimension, the patent reduces the vertical height requirement while maintaining precise electrical contact, thereby increasing packing density without sacrificing manufacturing precision
Data Source
AI summary
One method disclosed herein includes forming first and second transistor devices in and above adjacent active regions that are separated by an isolation region, wherein the transistors comprise a source/drain region and a shared gate structure, forming a continuous conductive line that spans across the isolation region and contacts the source/drain regions of the transistors and etching the continuous conductive line to form separated first and second unitary conductive source/drain contact structures that contact the source/drain regions of the first and second transistors, respectively. A device disclosed herein includes a gate structure, source/drain regions, first and second unitary conductive source/drain contact structures, each of which contacts one of the source/drain regions, and first and second conductive vias that contact the first and second unitary conductive source/drain contact structures, respectively.


